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ARM advanced microcontroller bus architecture (AMBA) specification.Rev 2.0.pdf
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AMBA ASB

4.8.13Data bus

The bidirectional data bus, BD[31:0], is used to transfer data between bus masters and slaves. The size and direction of the transfer is given by the control signals, as described in Address and control information on page 4-27.

The data bus must not be driven during the first BCLK LOW phase of a NONSEQUENTIAL transfer. It may be driven, by the appropriate master or slave, at all other times except reset.

During a write transfer:

the master drives the data bus during all phases of the transfer, except the first BCLK LOW phase of a NONSEQUENTIAL transfer

the slave does not drive the bus. During a read transfer:

The master does not drive the data bus.

The slave must drive the data bus during the last BCLK HIGH phase of the transfer. For the rest of the transfer, the slave may drive the data bus or leave it tristate, with the provision that it is not driven during the first BCLK LOW phase of a NONSEQUENTIAL transfer.

The following diagrams show some examples of how the data bus is driven.

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© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A

AMBA ASB

Figure 4-22 shows an example of a NONSEQUENTIAL write transfer.

BCLK

 

BTRAN[1:0]

N-TRAN

BA[31:0]

Address

BWRITE

 

BD[31:0]

Data

Figure 4-22 Nonsequential write transfer

The data bus is driven by the bus master, except for the BCLK LOW phase of the first cycle. Not driving the data bus at the start of NONSEQUENTIAL transfers provides a full phase of turnaround between different data bus drivers.

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

4-41

AMBA ASB

When a write transfer is extended using BWAIT, the data remains valid through the BCLK LOW phase of the extra cycles that are required to complete the transfer, as shown in Figure 4-23.

BCLK

 

BTRAN[1:0]

N-TRAN

BA[31:0]

 

BWRITE

 

BWAIT

 

BD[31:0]

 

Address

Data

Figure 4-23 Extended write transfer

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© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A

AMBA ASB

For SEQUENTIAL transfers the bus master may drive data during the LOW phase of BCLK at the start of the transfer, as shown in Figure 4-24. This is permitted as a phase of turnaround is not required for SEQUENTIAL transfers.

BCLK

 

BTRAN[1:0]

S-TRAN

BA[31:0]

Address

BWRITE

 

BD[31:0]

Data

Figure 4-24 Sequential write transfer

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

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