AMBA Test Methodology

6.2External interface

The external test interface consists of:

•a test clock

•three control signals

•a 32-bit test bus.

Only two dedicated signal pins are required (TREQA and TACK) to control the entry and exit of test mode. The remaining signals can be provided by reusing existing device pins.

6.2.1Test bus request A

TREQA is the test bus request A input signal and is required as a dedicated device pin.

During normal system operation the TREQA signal is used to request entry into the test mode. This will cause the test bus to become tristated, allowing test vectors to be applied.

During test this signal is used, in combination with TREQB, to indicate the type of test vector that will be applied in the following cycle.

6.2.2Test bus request B

TREQB is the test bus request B input signal.

During test this signal is used, in combination with TREQA, to indicate the type of test vector that will be applied in the following cycle.

6.2.3Test acknowledge

TACK is the test bus acknowledge output signal and is required as a dedicated device pin.

The test bus acknowledge signal gives external indication that the test bus has been granted and also indicates when a test access has completed. When TACK is LOW the current test vector must be extended until TACK becomes HIGH. The TREQA and TREQB signals are only sampled by the TIC when TACK is HIGH.

Table 6-1 and Table 6-2 show the operation of the TREQA, TREQB and TACK signals. The signals have different functions depending on whether or not test mode has been entered.

AMBA Test Methodology

Table 6-1 Test control signals during normal operation

6.2.4Test clock

TCLK is the test clock input signal.

In test mode, the internal bus clock is driven from the external TCLK source. This pin may be the normal clock oscillator source input or a port replacement signal. The system bus clock must not glitch when switching between normal and test mode.

On entry into test mode the TIC indicates that it has switched to the test clock input by asserting the TACK signal.

6.2.5Test bus

TBUS[31:0] is the 32-bit bidirectional test port.

The test bus is used as an input to apply address, control and write vectors. For read vectors the test bus is used as a device output. The test interface protocol ensures that a turnaround period is always provided when changing the direction of the test bus.