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ARM advanced microcontroller bus architecture (AMBA) specification.Rev 2.0.pdf
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AMBA APB

5.7Interfacing APB to ASB

Interfacing the AMBA APB to the ASB is described in:

Write transfer

Read transfer on page 5-21.

5.7.1Write transfer

Figure 5-15 illustrates how an interface from ASB to APB can be constructed. The write transfer can occur with zero wait-states, although an additional wait state is required for a burst of writes.

BCLK

BA

Addr 1

BWRITE

 

BD

Data

BWAIT

 

PADDR

Addr 1

PWRITE

 

PSEL

 

PENABLE

 

PWDATA

Data 1

 

Figure 5-15 Write transfer from ASB

5-20

© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A

AMBA APB

5.7.2Read transfer

The read transfer will always require a single wait state (see Figure 5-16). In systems with a high clock frequency it may be necessary to insert an additional wait state to ensure that the read data has adequate time to pass through the bridge and become valid on the ASB.

BCLK

BA

Addr 1

 

BWRITE

 

BD

Data

 

BWAIT

 

PADDR

Addr 1

PWRITE

 

PSEL

 

PENABLE

 

PRDATA

Data 1

 

 

Figure 5-16 Read transfer to ASB

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

5-21