- •Table of Contents
- •1.1. Introduction
- •1.2. Problems
- •2. Behavior and Structure models
- •2.1. Introduction
- •2.2. Problems
- •3. State Machines and Programmable Logic Devices
- •3.1. Introduction
- •3.2. Mealy and Moore State Machines
- •3.4. Problems
- •4. Digital Device Modeling
- •4.1. Introduction
- •4.2. SRAM Memory
- •4.3. VHDL SRAM Memory Design
- •4.5. Problems
- •5.1. Introduction
- •5.2. VHDL Features
- •5.3. ALU Functions
- •5.6. Problems
- •6.1. Introduction
- •6.2. Instruction Set Architecture (ISA)
- •6.3. A Computer Architecture Implementation
- •6.5. Problems
- •7. Appendices
- •7.1. Install Warp on PC
Digital Design VHDL Laboratory
3.State Machines and Programmable Logic Devices
Pepe, 4/5/96. 5/23/96
state_clocking: process(clk) begin if (clk'event and clk='1') then
present_state <= next_state; end if;
end process state_clocking;
moore_output: process(present_state) begin if (present_state=HIGH1) then
output <= '1'; else
output <= '0'; end if;
end process moore_output;
end moore_machine;
Listing 3-2. Moore Machine VHDL Code
3.4 Problems
1)Convert the Moore machine in Figure 3-7 into a Mealy machine. Implement the Mealy machine in VHDL and simulate it with Cypress NOVA simulator.
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0/1 |
Start |
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q1 |
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q0 |
1/0 |
0/0 |
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1/0 |
1/1 |
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q2 |
Figure 3-7. Question #1
2)Simulate the state machine shown in Figure 3-8 with VHDL and describe what it does (Hint: See next question).
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0 |
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q0/0 |
q1/1 |
q2/2 |
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0 |
Start |
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Figure 3-8. Question #2
3)Design a Mealy state machine that computes the remainder of value 5 instead 3. Draw the state diagram and simulate it with VHDL. Test the machine using input 3, 4, 5, 6, 76, and 101.
4)Design the state machine of the state flow diagram in Figure 3-9 and the output table in Table 3-3.
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Copyright 1996, CERL / EE, V1.00 |
frame
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IDLE |
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/frame |
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f |
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r |
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DECODE |
am |
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e |
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hit |
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/hit |
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/frame |
/frame |
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XFER |
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BUSY |
XFER2
Figure 3-9. State Flow Diagram
Digital Design VHDL Laboratory 3.State Machines and Programmable Logic Devices Pepe, 4/5/96. 5/23/96
Table 3-3. |
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State / Output |
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OE |
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GO |
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ACT |
IDLE |
0 |
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0 |
0 |
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DECODE |
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0 |
0 |
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0 |
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BUSY |
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0 |
1 |
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0 |
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XFER |
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1 |
1 |
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1 |
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XFER2 |
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0 |
1 |
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1 |
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Copyright 1996, CERL / EE, V1.00 |