12.Phase Lock Loops

REFERENCES 277

PROBLEMS

12.1A phase lock loop can be described in the frequency domain in terms of the input and output phase angles shown in Fig. 12.7. The input phase is

Q1 s D a C b/s2. The filter transfer function is

1 C sCR2

F s D

1 C sC R1 C R2

(a)What is the steady state phase error?

(b)What is the steady state phase error if the capacitance C D 1?

REFERENCES

1.A. J. Viterbi, Principles of Coherent Communication, New York: McGraw-Hill, 1966.

2.U. L. Rhode, Microwave and Wireless Synthesizers: Theory and Design, New York: Wiley, 1997.

3.J. A. Crawford, Frequency Synthesizer Design Handbook, Norwood, MA: Artech House, 1994.

4.U. L. Rhode, et al., Communications Receivers, 2nd ed., New York: McGraw-Hill, 1996.

5.B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, New York: IEEE Press, 1996.