- •Contents
- •Introduction
- •1.1 Scope
- •Figure 1-1: Main system blocks
- •1.2 Summary
- •See Chapter 2, Memory Map.
- •Level sensitive interrupts.
- •Programmed interrupt source available
- •See Chapter 3, Interrupt Controller.
- •Free-running or periodic timer modes.
- •See Chapter 4, Timer.
- •See Chapter 5, Communications Channel.
- •"Wait for Interrupt" Pause mode.
- •See Chapter 6, Remap and Pause.
- •Memory Map
- •2.1 Introduction
- •2.2 Memory Map Base Addresses
- •Interrupt Controller
- •3.1 Introduction
- •Figure 3-1: FIQ and IRQ interrupts
- •3.2 Interrupt Control
- •Figure 3-2: Interrupt Controller Bit Slice
- •3.3 Interrupt Controller Register Descriptions
- •3.5 Interrupt Controller Memory Map
- •Timer
- •4.1 Introduction
- •4.2 Timer Operation
- •Figure 4-1: Timer Block Diagram
- •Figure 4-2: Timer Pre-scale Unit
- •4.3 Timer Register Descriptions
- •4.3.1 Load Register
- •4.3.2 Value
- •4.3.3 Clear
- •4.3.4 Control Register
- •Figure 4-3: Timer Register Bit Positions
- •1—Timer Enabled
- •1—Periodic Timer Model
- •Clock
- •Divided by
- •Stages of
- •Pre-scale
- •Undefined
- •Table 4-1: Bits 3 – 2: Prescale bits
- •4.4 Timer Memory Map
- •Address
- •Read Location
- •Write Location
- •TimerBase
- •Timer1Load
- •Timer1Load
- •TimerBase + 0x04
- •Timer1Value
- •Reserved
- •TimerBase + 0x08
- •Timer1Control
- •Timer1Control
- •TimerBase + 0x0C
- •Reserved
- •Timer1Clear
- •TimerBase + 0x10
- •Reserved
- •Reserved
- •TimerBase + 0x20
- •Timer2Load
- •Timer2Load
- •TimerBase + 0x24
- •Timer2Value
- •Reserved
- •TimerBase + 0x28
- •Timer2Control
- •Timer2Control
- •TimerBase + 0x2C
- •Reserved
- •Timer2Clear
- •TimerBase + 0x30
- •Reserved
- •Reserved
- •Table 4-2: Timer Address Map
- •Communications Channel
- •5.1 Introduction
- •Remap and Pause
- •6.1 Introduction
- •6.2 Pause
- •6.4 Reset Status
- •6.5 Clear Reset Memory Map
- •6.6 Remap and Pause Memory Map
- •Address
- •Read Location
- •Write Location
- •RemapBase
- •Reserved
- •Pause
- •RemapBase + 0x10
- •Identification
- •Reserved
- •RemapBase + 0x20
- •Reserved
- •ClearResetMap
- •RemapBase + 0x30
- •ResetStatus
- •ResetStatusSet
- •RemapBase + 0x34
- •Reserved
- •ResetStatusClear
- •Table 6-1: Remap and Pause Memory Map
Timer
4.3Timer Register Descriptions
4.3.1Load Register
Read/write. The Load register contains the initial value of the timer and is also used as the reload value in periodic timer mode. When writing to this register the top 16 bits should be written as 0 and when reading the top 16 bits will be undefined.
4.3.2Value
Read only. The Value location gives the current value of the timer. When reading this location the top 16 bits are read as undefined.
4.3.3Clear
Write only. Writing to the Clear location clears an interrupt generated by the counter timer.
4.3.4Control Register
Read/Write. The Control register provides enable/disable, mode and pre-scale configurations for the timer.
Figure 4-3: Timer Register Bit Positions and Table 4-1: Bits 3 – 2: Prescale bitsbelow define the operation of the Control register.
31 |
8 |
7 |
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6 |
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5 |
4 |
3 |
2 |
1 |
0 |
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0 |
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Ena- |
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Mode |
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0 |
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Pre-scale |
0 |
0 |
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Figure 4-3: Timer Register Bit Positions |
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Bit 7 – Enable Bit |
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0—Timer Disabled |
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1—Timer Enabled |
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Bit 6 – Mode Bit |
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0—Free-running Model |
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1—Periodic Timer Model |
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Bits 3 – 2: Pre-scale Bits |
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See Table 4-1: Bits 3 – 2: Prescale bitson |
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page 4-6 |
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Reference Peripherals Specification |
4-5 |
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ARM DDI 0062D |
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Open Access