- •Contents
- •Introduction
- •1.1 Scope
- •Figure 1-1: Main system blocks
- •1.2 Summary
- •See Chapter 2, Memory Map.
- •Level sensitive interrupts.
- •Programmed interrupt source available
- •See Chapter 3, Interrupt Controller.
- •Free-running or periodic timer modes.
- •See Chapter 4, Timer.
- •See Chapter 5, Communications Channel.
- •"Wait for Interrupt" Pause mode.
- •See Chapter 6, Remap and Pause.
- •Memory Map
- •2.1 Introduction
- •2.2 Memory Map Base Addresses
- •Interrupt Controller
- •3.1 Introduction
- •Figure 3-1: FIQ and IRQ interrupts
- •3.2 Interrupt Control
- •Figure 3-2: Interrupt Controller Bit Slice
- •3.3 Interrupt Controller Register Descriptions
- •3.5 Interrupt Controller Memory Map
- •Timer
- •4.1 Introduction
- •4.2 Timer Operation
- •Figure 4-1: Timer Block Diagram
- •Figure 4-2: Timer Pre-scale Unit
- •4.3 Timer Register Descriptions
- •4.3.1 Load Register
- •4.3.2 Value
- •4.3.3 Clear
- •4.3.4 Control Register
- •Figure 4-3: Timer Register Bit Positions
- •1—Timer Enabled
- •1—Periodic Timer Model
- •Clock
- •Divided by
- •Stages of
- •Pre-scale
- •Undefined
- •Table 4-1: Bits 3 – 2: Prescale bits
- •4.4 Timer Memory Map
- •Address
- •Read Location
- •Write Location
- •TimerBase
- •Timer1Load
- •Timer1Load
- •TimerBase + 0x04
- •Timer1Value
- •Reserved
- •TimerBase + 0x08
- •Timer1Control
- •Timer1Control
- •TimerBase + 0x0C
- •Reserved
- •Timer1Clear
- •TimerBase + 0x10
- •Reserved
- •Reserved
- •TimerBase + 0x20
- •Timer2Load
- •Timer2Load
- •TimerBase + 0x24
- •Timer2Value
- •Reserved
- •TimerBase + 0x28
- •Timer2Control
- •Timer2Control
- •TimerBase + 0x2C
- •Reserved
- •Timer2Clear
- •TimerBase + 0x30
- •Reserved
- •Reserved
- •Table 4-2: Timer Address Map
- •Communications Channel
- •5.1 Introduction
- •Remap and Pause
- •6.1 Introduction
- •6.2 Pause
- •6.4 Reset Status
- •6.5 Clear Reset Memory Map
- •6.6 Remap and Pause Memory Map
- •Address
- •Read Location
- •Write Location
- •RemapBase
- •Reserved
- •Pause
- •RemapBase + 0x10
- •Identification
- •Reserved
- •RemapBase + 0x20
- •Reserved
- •ClearResetMap
- •RemapBase + 0x30
- •ResetStatus
- •ResetStatusSet
- •RemapBase + 0x34
- •Reserved
- •ResetStatusClear
- •Table 6-1: Remap and Pause Memory Map
Reference Peripherals Specification
Reference Peripherals
Specification
Document number: |
ARM DDI 0062D |
Issued: |
May 1996 |
Copyright Advanced RISC Machines Ltd (ARM) 1996
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Open Access
Proprietary Notice
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Neither the whole nor any part of the information contained in, or the product described in, this manual may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this manual is subject to continuous developments and improvements. All particulars of the product and its use contained in this manual are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties
or merchantability, or fitness for purpose, are excluded.
This manual is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this manual, or any error or omission in such information, or any incorrect use of the product.
Key
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Information status is one of: |
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Preliminary |
Current information on a product under development |
Final |
Complete information on a developed product |
Change Log
Issue |
Date |
By |
Change |
A |
July 1995 |
BM |
Released in Word as “Reference |
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Microcontroller Specification” |
B |
April 1996 |
BM, JEU |
Converted to Frame and renamed “Reference |
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Peripherals Specification” |
C |
May 1996 |
BM, JEU |
Minor Edits |
D |
May 1996 |
BM,JEU |
Minor Edits |
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Reference Peripherals Specification |
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ARM DDI 0062D |
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Open Access
Contents
1 |
Introduction |
1-1 |
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1.1 |
Scope |
1-2 |
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1.2 |
Summary |
1-3 |
2 |
Memory Map |
2-1 |
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2.1 |
Introduction |
2-2 |
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2.2 |
Memory Map Base Addresses |
2-3 |
3 |
Interrupt Controller |
3-1 |
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3.1 |
Introduction |
3-2 |
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3.2 |
Interrupt Control |
3-4 |
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3.3 |
Interrupt Controller Register Descriptions |
3-6 |
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3.4 |
Interrupt Controller Defined Bits |
3-8 |
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3.5 |
Interrupt Controller Memory Map |
3-9 |
4 |
Timer |
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4-1 |
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4.1 |
Introduction |
4-2 |
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4.2 |
Timer Operation |
4-3 |
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4.3 |
Timer Register Descriptions |
4-5 |
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4.4 |
Timer Memory Map |
4-7 |
Reference Peripherals Specification
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ARM DDI 0062D
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5 |
Communications Channel |
5-1 |
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5.1 |
Introduction |
5-2 |
6 |
Remap and Pause |
6-1 |
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6.1 |
Introduction |
6-2 |
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6.2 |
Pause |
6-3 |
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6.3 |
Identification Register |
6-4 |
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6.4 |
Reset Status |
6-5 |
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6.5 |
Clear Reset Memory Map |
6-6 |
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6.6 |
Remap and Pause Memory Map |
6-7 |
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