Microcontrollers in Practice (Mitescu M., 2005)

4.6 Exercises

X 4.1

Draw the schematic of a SPI link between a HC11E9 (master) and an AT90S8535 (slave).

X 4.2

Draw the schematic of a circuit that expands the I/O space with 16 input lines and 16 output lines. Describe how would you connect such circuit to a HC11E9 microcontroller.

5

Using The I2C Bus

5.1 In this Chapter

This chapter continues the presentation of the serial communication interfaces with the description of the I2C bus. It contains suggestions about a possible software implementation of the I2C protocol, and examples on how to connect a 24×256 I2C memory to a microcontroller.

5.2 The Principles of Implementation of the I2C Bus

An I2C bus (Inter IC bus) consists of two signal conductors named SDA (Serial Data) and SCL (Serial Clock) that interconnect at least two devices. Each of the devices connected to the bus must be identified by a unique address. In principle, any of the devices connected to the bus can transmit and receive data. The device that initiates and completes a bus transfer, and generates the transfer clock, is named the MASTER.

As any of the devices connected on the bus can become MASTER at a certain time, the SDA and SCL lines must both be bi-directional. In practice open drain or open collector lines are used. The pull-up resistors have usual values between 2 K and 10 K, depending on the chosen communication speed (at high speed, the pull-up resistor has a smaller value). The idle status of the SDA and SCL lines is HIGH. A bus transfer sequence comprises the following steps:

1.The MASTER device generates a START condition on the bus.

2.The MASTER device generates eight SCL pulses controlling the SDA line in such a way that it transmits a byte which contains the SLAVE’s device address and codes the type of the transfer (writing or reading). The receiver samples the SDA line while the SCL line is HIGH, and therefore data must be stable while the SCL is HIGH. SDA may change status only when SCL is LOW.

3.The MASTER device sends a ninth clock on the SCL line, while releasing the SDA data line. The device that recognized its address in the first byte transmitted

62 5 Using The I2C Bus

by the MASTER pulls the line LOW for the period of this clock, thus generating an ACK (acknowledge) condition.

4.The MASTER device continues to generate packages of nine SCL pulses, while the SDA is controlled either by the MASTER or by the SLAVE, depending on the type of the transfer in course. After each byte transmitted, the receiver generates an ACK condition. If the MASTER is the receiver (for example during a SLAVE byte read operation), then THE MASTER will generate ACK.

5.The process continues until MASTER generates a STOP condition and the bus returns to the idle status.

The following paragraphs describe each of the above steps.

5.2.1 The Start Transfer Condition

The START transfer condition consists of a HIGH to LOW transition of the SDA line, while the SCL clock line is maintained HIGH. The waveform corresponding to this condition is presented in Fig. 5.1.

SDA

SCL

Data may change

START condition

IDLE bus

Fig. 5.1. The START TRANSFER condition on the I2C bus

5.2.2 The Data Transfer on the I2C BuS

The actual data transfer, after a START condition, begins after the SCL line is brought to LOW. At this moment, the state of the SDA data line may be modified and set to the value of the bit that follows in the transmission sequence. The receiver samples the SDA line only after the SCL line is raised HIGH. Figure 5.2 shows the waveforms for SDA and SCL for a transmission sequence containing the START condition, and the transmission of the four data bits in the sequence 1101.

The first bit transmitted is the most significant bit (MSB) of each byte.

5.2.3 The ACK Bit

After the transmission of a byte (eight SCL pulses), the MASTER device releases the SDA line and generates a ninth SCL clock. When the SCL line becomes 1, the

Fig. 5.2. Example of waveform for data transmission on the I2C bus

SLAVE device pulls SDA to LOW, confirming by this the reception of the byte. In all situations the data line is controlled by the receiver during the ACK bit time. In case of a read byte operation, the device that sends ACK is the receiver, i.e. the MASTER device.

5.2.4 The STOP Condition

A STOP transmission condition is generated when a LOW to HIGH transition of the SDA line occurs while the SCL line is HIGH. After the STOP condition, both SDA and SCL bus lines return to the idle state, and a new transmission must be preceded by a START sequence.

SDA

SCL

STOP Condition

Fig. 5.3. The STOP TRANSFER condition on the I2C bus

In practice, the I2C protocol is more complicated, meaning that it allows operation in multimaster mode. In this case, an arbitration mechanism is required to allocate the bus in situations when two or more devices try to become MASTER at the same time. In this book only single-master I2C buses are discussed.

5.3 A Software Implementation of the I2C Protocol

There is a variety of circuits available, which are designed to communicate with a microcontroller via the I2C bus: memories, LCD displays, A/D and D/A converters, etc. Usually these are delivered in small capsules, with extremely low power consumption and require only two I/O lines of the microcontroller for connection.

64 5 Using The I2C Bus

Besides that, the access to any device connected to the I2C bus can be controlled by a library of reusable software modules. All these advantages recommend the I2C devices for many microcontroller applications, especially when the use of an expanded microcontroller structure is difficult or impossible.

The SDA and SCL lines are controlled by software through simple subroutines. The following example, written for HC11, illustrates the generation of the START condition on the I2C bus:

Similarly, a STOP condition is generated in the following way:

5.4 Accessing 24C256 Memory Devices

In the example presented in Fig. 5.4, the two 24Cxx circuits have the address lines A0, A1, A2, hardwired to different values. In this configuration, the microcontroller is, obviously, the MASTER device. After the START sequence, the microcontroller sends a byte that contains the address of the SLAVE device and the type of the operation: read or write. The structure of this byte is as follows:

R/W\ = 1 indicates that a read operation follows.

R/W\ = 0 indicates a memory write operation

The upper-nibble of this byte is always 1010 for this type of memory. The A2, A1, A0 bits contain the SLAVE’s device address. After the transmission of the byte with the SLAVE address, the device that recognizes its address pulls the SDA line LOW, for the duration of the ninth clock, thus generating the ACK condition.

In the case of a write operation to the 24C256 memory, after the byte containing the SLAVE address, the microcontroller sends two bytes containing the address of

Fig. 5.4. Connecting I2C memory devices to a microcontroller

the location that is to be written, followed by a byte containing the value to be written in the memory. After each received byte, the memory sends an ACK bit, and, after the last ACK, the microcontroller generates a STOP condition to complete the write operation. If, instead of generating a STOP condition, the microcontroller sends a new byte, this will be written in the memory to the next address. In this manner, up to 64 bytes can be written consecutively. This type of operation is named “page write mode”.

To read a byte from a random address (random read operation) the microcontroller initiates a write sequence, in which it sends the byte with the SLAVE address, followed by two bytes with the address of the location that is to be read. Then, a new START is generated, followed by the SLAVE address byte, with the R/W\ bit set to 1, indicating a read operation. After the ACK is received from the SLAVE, the microcontroller sends eight more SCL pulses to get the read byte from memory, then it generates a STOP condition.

If, instead of generating the STOP condition, the microcontroller sends an ACK, followed by eight SCL clock pulses, it reads the byte from the next address. The process continues in the same way. At each ACK generated by the microcontroller, the internal address counter of the memory is incremented, and the process continues with reading of the next byte. The process completes when MCU generates a STOP condition.

The accompanying CD contains examples of subroutines to access I2C memories, written for HC11 and 8051.

66 5 Using The I2C Bus

5.5 Exercises

SX 5.1

Is the I2C communication synchronous or asynchronous?

Solution

Since there is a dedicated line for transmission of the clock, it follows that the transmission on the I2C bus is synchronous. The START and STOP conditions delimit data packets, not data bytes as in the case of the asynchronous communication.

SX 5.2

SPI and I2C are both synchronous communication methods. Which one is faster?

Solution

In theory at least, SPI is faster, because it is full duplex. At a given frequency of the transmission clock, the data volume transmitted on SPI is double the volume transmitted on I2C, because data is transmitted in both directions on the MOSI and MISO lines.

SX5.3

Draw the waveforms for the SDA and SCL in case of the transmission of a START transfer condition, followed by the transmission of the byte with the value $A2 = 10100010b, and ACK.

Solution

See Fig. 5.5 for the idealized waveforms of SDA and SCL for this example.

Fig. 5.5. Solution of the exercise SX 5.3

6

Using the MCU Timers

6.1 In this Chapter

This chapter contains a description of the timer system of microcontrollers, including the general-purpose timer, the PWM timer, and the watchdog.

6.2 The General Structure and Functions of the Timer System

Timing is essential for the operation of microcontroller systems, either for generating signals with precisely determined duration, or for counting external events. For this reason, the timer subsystem is present in all microcontroller implementations, and covers a wide range of functions including:

•Generation of precise time intervals

•Measurement of duration of external events

•Counting external events.

Most microcontrollers are provided with dedicated timers, or use the generalpurpose timer to implement the following additional functions:

•Real time clock

•Generation of Pulse Width Modulated (PWM) signals

•Watchdog for detecting program runaway situations.

Although there are significant variations between different implementations of the general-purpose timer in different microcontrollers, there are many similarities in the principles of operation and the structure of the timer subsystem.

Figure 6.1 shows a general block diagram of the timer system, illustrating the principles of implementation of most MCU timers.

The central element of the timer subsystem is a counter, TCNT (8 or 16-bits in length), which may be read or (sometimes) written by software. The clock for TCNT is obtained either from the system clock, divided by a programmable prescaler, or an external clock applied to one of the MCU pins. The software control upon the timer is

68 6 Using the MCU Timers

Fig. 6.1. General block diagram of the timer subsystem

performed by means of the control register TCTL and information regarding various events related to the timer may be read from the status register TFLG.

Several operating modes are possible for the timer:

Timer overflow. In this mode, the event of interest is when the TCNT counter reaches its maximum count and returns to zero on the next clock pulse. The overflow signal that marks this event is applied to the interrupt control logic (ICL), which may generate an interrupt request to the CPU.

The time interval between two successive overflows is controlled either by modifying the frequency of the input clock applied to TCNT, or by writing to TCNT an initial value for counting.

•Input capture. In this operating mode, the contents of TCNT at the moment of the occurrence of an external event, defined by the edge of an input signal, is transferred in a capture register (ICR), and an interrupt request may be generated. By comparing two consecutive values capture by the ICR, it is possible to determine the time interval between the two external events.

•Output compare. In this operating mode, the contents of TCNT are continuously compared by hardware to the contents of the OCR (Output Compare Register) by means of the digital comparator COMP. When the contents of the two registers match, an interrupt request may be generated. Optionally, the compare match can be programmed to change the status of one or more output lines.

•External events counter. In this operating mode, the input of TCNT is connected to one of the MCU input lines, and TCNT counts the pulses associated with the external events. The software is informed about the recorded number of external events by reading TCNT.

6.3 Distinctive Features of the General-Purpose Timer of HC11

The 16-bit TCNT counter of HC11 can count on the internal clock only, and only upwards. It can be read by software, but cannot be cleared or written. The prescaler is a programmable 4-bit counter, which divides the system clock E by 1, 4, 8, or 16.

There are four 16-bit output compare registers (OCR), called TOC1, TOC2, TOC3, and TOC4, three input capture register (ICR), called TIC1, TIC2, and TIC3, and an additional register, which can be configured by software to operate as a fifth OCR register, under the name of TOC5, or as a fourth input capture register TIC4. The various timer functions are associated with the I/O lines of PORT A, as shown in Table 6.1.

Table 6.1. Alternate functions of the I/O lines of PORT A

6.3.1 The Control and Status Registers of the HC11 Timer

Although the counter TCNT, and the prescaler are unique, the presence of the eight ICR/OCR registers, each having distinct status flags, associated I/O lines, along with the possibility to generate distinct interrupt requests, makes the HC11 timer act as eight different timers. Therefore, the number of control and status registers associated with the timer is higher than the average number of registers of a peripheral interface. For clarity of the presentation, the registers of the timer system are described in connection with the basic operating modes of the timer.

6.3.1.1 The Timer Overflow Operating Mode

The prescaler is controlled by the bits PR1:PR0 in register TMSK2 (Timer Interrupt Mask Register 2, bits [1:0]), which select the dividing rate of the system clock E to obtain the clock for TCNT.

After the transition of the counter TCNT from $FFFF to $0000, a flag is set by hardware. This is the TOF (Time Overflow Flag) bit in the status register TFLG2 (bit 7). If the associated local interrupt mask, TOI (Time Overflow Interrupt enable) from register TMSK2 (bit 7), is set, then an interrupt request is generated.

Note that the interrupt service routine must clear TOF by writing 1 in the corresponding position of the TFLG2 register.