Microcontrollers in Practice (Mitescu M., 2005)

Current loop

Older technique of encoding information on serial communication lines. Typical values for the switched currents are 20 mA for an “IDLE,” “MARK,” or “1” condition and 0 mA for a “START,” “SPACE,” or “0” condition. This type of connection has high noise immunity and built-in ground loop isolation. The disadvantage is that the data rate is usually limited to less than 19.2 kbps.

See also: Asynchronous communication, RS232, RS422, RS485

DAC

Acronym for Digital-to-Analog Converter. A circuit that generates an analog signal having amplitude proportional with the value of a binary number received as input.

See also: ADC, Resolution

Data Bus

The bus (physical connection between the CPU and other resources of a computer system) that carries data. Note that some computer system can have more than one data buses.

See also: Bus, Address bus, Architecture, Harvard, Von Neumann

Data direction register

A register, associated with an input/output port, used to configure each individual line of the port as an input or output line.

See also: I/O line, I/O port

Data memory

Read/write memory area used to store variables in a computer system.

See also: Architecture, Memory, RAM, ROM

Differential communication

Technique of communication based on the use of two conductors to transmit each digital signal, the logic levels being defined by the relative difference of potential between the two conductors. The line driver of the transmitter controls the voltage levels on the two conductors, so that the difference of potential between them is positive for logic 1 and negative for logic 0.

See also: Current loop, RS232, RS422, RS485

206 Appendices

EEPROM

Acronym for Electrically Erasable Programmable Read Only Memory. A special type of non-volatile memory that can be erased by exposing it, in certain conditions, to an electrical voltage higher than the normal operating voltage.

See also: RAM, ROM, Flash memory

Flash memory

Type of erasable non-volatile memory, very similar to EEPROM. The main difference between the two types is that EEPROM must be written one byte at a time, while the flash memory allows writing of blocks of data, which leads to faster write operations.

See also: RAM, ROM, EEPROM

Framing error

Error condition, specific for asynchronous serial communications, occurring when an invalid stop bit is detected.

See also: Asynchronous communication, Start bit, Stop bit.

Harvard

Computer architecture characterized by the presence of different buses for program memory and data memory. This leads to higher processing speed.

See also: Von Neumann

I2C bus

Acronym for Inter IC bus. This type of bus consists of two signal conductors named SDA (Serial Data) and SCL (Serial Clock) that interconnect at least two devices.

See also: Bus

Intel hex format

Special text file format, introduced by Intel Corporation, to encode the executable code generated by cross-assemblers or cross-compilers. Unlike binary files, the Intel hex files contain information about the address where the code must be loaded in the program memory and special checksums for error detection when the file is transmitted over serial communication lines.

See also: Motorola S file format

Interrupt

A mechanism that allows an external event to temporarily put on hold the normal execution of the program, forcing the execution of a specific subroutine. Once the interrupt service subroutine completes, the main program continues from the point where it was interrupted.

See also: Interrupt vector, Interrupt service routine

Interrupt service routine

The interrupt service routine (ISR) is a program sequence similar to a subroutine, executed every time the associated interrupt occurs. Unlike “regular” subroutines, the ISR ends with a special instruction called Return from Interrupt (RTI, RETI). The starting address of the interrupt service routine is defined by the interrupt vector.

See also: Interrupt, Interrupt vector

Interrupt vector

Reserved memory area, associated with each interrupt source, that contains either the address of the interrupt service routine, or a jump instruction to this routine.

See also: Interrupt, Interrupt service routine

Instruction

Basic element of a program, which encodes an elementary operation. A program is a logic sequence of instructions. The CPU reads the code of each instruction from the program memory, decodes and executes it, then fetches the next instruction in sequence.

See also: Program memory

I/O line

Input/output line. A mechanism for a computer system to interact with the outside world. An input line is used to sense the electrical level of an external signal, and an output line modifies its electrical status as directed by the program. In many cases, the I/O lines can be configured by the program to act as inputs or outputs.

See also: I/O port, Data direction register, Peripheral interface

I/O port

A group of I/O lines that can be accessed simultaneously. The number of lines of an I/O port depends on the width of the data bus, i. e. the number of data bits that can be transferred in a certain time on the data bus.

See also: I/O line, Data bus

208 Appendices

ISP

Acronym for In-System Programming. A technique to program the internal program memory of some microcontrollers, by means of a specially designed interface.

See also: Program memory

Master–slave protocol

Communication protocol in which one MASTER device controls one or more SLAVE devices.

MCU

Acronym for Microcontroller Unit. Designates a single-chip computer, a structure that integrates a CPU, certain amounts of program memory and data memory, and a number of peripheral interfaces, all in one chip.

See also: CPU, ROM, RAM, Memory, Architecture, Peripheral interface

Memory

A device designed to store data. The simplest memory cell is the D-type flip–flop. In a microcontroller system, the memory is organized as an array of locations, each having a distinct address. The number of bits of each location is determined by the width of the data bus.

See also: Data memory, Program memory, RAM, ROM, Architecture

Memory map

A list showing how the addresses of an address space are assigned to resources.

See also: Address space, Architecture, Memory

Motorola S File format

Special text file format, introduced by Motorola, to encode the executable code generated by cross-assemblers or cross-compilers.

One distinctive feature of these files is that all the lines in this type of file start with the letter S. Unlike binary files, the Motorola S files contain information about the address where the code must be loaded in the program memory, and special checksums for error detection when the file is transmitted over serial communication lines.

See also: Intel hex file format

Network

A structure consisting in a number of devices interconnected in a way that allows data exchange between them, according to a set of rules, known as communication protocol.

See also: Protocol, Master–slave protocol

Overrun error

In a communication system, this error occurs at the receiver when a new character is received before the previous character has been handled.

See also: Framing error

Parity bit

Error detection technique consisting in adding an extra bit to each group of bits transmitted, so that the group always has an odd or even number of 1’s. Usually the parity is checked at the byte level.

See also: CRC, Framing error, Overrun error

Peripheral interface

A circuit designed to sense/drive a number of I/O lines in order to provide a computer system with the capability to communicate with external equipment.

See also: I/O line, I/O port.

Prescaller

Programmable counter used by some peripheral interfaces to divide the system clock to provide a variable frequency clock to the interface.

See also: Peripheral interface

Program memory

Non-volatile memory used to store program information. The program memory is connected to the CPU through address and data buses.

See also: Memory, ROM, Flash memory, Address bus, Data bus, Architecture

Protocol

In a communication system or network, the protocol is a set of rules defining the structure of the data packets transmitted, and the conditions of access to the communication bus for each device in the system.

See also: Master–slave protocol

PWM

Acronym for Pulse Width Modulation. Some microcontrollers contain a special interface able to generate PWM signals with programmable frequency and duty cycle.

See also: Timer

210 Appendices

RAM

Acronym for Random Access Memory. Typical read/write memory used to store variables (data memory). RAM memory is volatile, i. e. it loses its contents at powerdown.

See also: Memory, Data memory, ROM, EEPROM, Flash memory

Register

Memory location, identified by a unique address, associated with particular control or status information regarding a peripheral interface or a part or function of the CPU.

See also: Memor, Peripheral interface

Resolution

The number of bits of an ADC or DAC circuit, which directly determines the number of quantization levels of the analog signal; e. g. a 10-bit ADC can distinguish 210 values of amplitude of the analog input.

See also: ADC, DAC

ROM

Acronym for Read Only Memory. Non-volatile memory used to store program or data constants.

See also: Memory, Data memory, Program memory, RAM, EEPROM, Flash memory.

RS232

Recommended Standard of EIA organization, for point-to-point serial communication, where signals are carried as single voltages, referred to a common ground. The voltage levels associated with the logic levels 0 and 1 are as follows:

–For logic 0, the voltage on the communication line must be in the range +6 V to 15 V.

–For logic 1, the voltage must be in the range −6 V to −15 V.

See also: Differential communication, RS422, RS485

RS422

Recommended Standard for point-to-point differential communication, where two conductors are used to transmit each digital signal, the logic levels being defined by the relative difference of potential between the two conductors.

See also: Differential communication, RS485

RS485

Recommended Standard for multipoint differential communication. RS485 allows up to 32 transmitters to be connected to the same twisted pair of conductors. Therefore, each RS485 transmitter must be able to be virtually disconnected from the bus, by driving its output into a high-impedance status.

See also: Differential communication, RS422

SAR

Successive Approximation Register. Technique used by some ADC circuits to obtain the digital value of the analog input, by successively comparing the analog input with an analog value obtained by converting to analog the contents of the register that stores the results of comparisons.

See also: ADC, DAC

SCI

Serial Communication Interface. Peripheral interface designed to allow asynchronous serial communication between computer systems and peripheral equipment.

See also: Asynchronous communication, UART, Start bit, Stop bit, Framing error

S&H circuit

Acronym for sample & hold circuit. A circuit used by some ADC circuits to hold the instantaneous values of the analog input, for the duration of the conversion process.

See also: ADC

SPI

Synchronous Peripheral Interface. Particular master–slave communication interface, where the master device generates a common clock used by the transmitter and receiver to serially shift data in both directions.

See also: Master–slave communication, Synchronous communication

Stack

A data structure having Last In First Out (LIFO) access type. In practice, in most cases, the stack is a reserved area of the system RAM memory, addressed by a special register, called the Stack Pointer (SP).

See also: Stack Pointer

212 Appendices

Stack pointer

A register used to address the stack. The stack pointer points to the top of the stack. Depending on the implementation, the top of the stack can be defined as the first empty location in the stack, or as the most recently pushed data.

See also: Stack

Start bit

In asynchronous serial communication, before the actual data transmission begins, the transmission line is pulled to the polarity opposite to the polarity of the idle line, for a duration of a bit time. This technique is destined to provide a means to synchronize the receiver.

See also: Asynchronous communication, Stop bit

Stop bit

In asynchronous serial communication, after the transmission of the data bits and any parity bit, the polarity of the transmission line is returned to the polarity of the idle line for the duration of a bit time.

See also: Asynchronous communication, Start bit

Synchronous communication

Communication technique that requires a common clock signal for the transmitter and receiver(s) in order to coordinate (synchronize) their activity.

See also: Asynchronous communication, SCI, SPI

UART

Acronym for Universal Asynchronous Receiver Transmitter. Interface circuit for asynchronous communication.

See also: Asynchronous communication, SCI

Von Neumann

Computer architecture characterized by common address and data buses for program memory and data memory.

See also: Architecture, Harvard

A.2 Description of the Registers of 68HC11F1

Note

The register block of 68HC11F1 is located by default in the address range $1000– $105F. The whole block can be relocated by writing the control bits [REG3–REG0] in the INIT register. Consult the data sheets for details on the registers of other HC11 family members.