Microcontrollers in Practice (Mitescu M., 2005)

For the same safety reason, the control bit that enables the whole watchdog system is the NOCOP bit in the CONFIG register. As mentioned before, CONFIG is a non-volatile, EEPROM type register, which can only be modified using special programming sequences, as described in Chap. 8.

A special register COPRST has been provided to clear the watchdog counter. This is cleared by writing bytes $55 and $AA, in this order, to COPSRT:

6.7.2 The Watchdog of AT90S8515

The watchdog of the AVR family counts on a separate clock, distinct from the MCU clock. This is generated by an internal RC oscillator and has an approximate frequency of 1 MHz at VCC = 5 V.

The software control on the watchdog system is performed by means of the WDCTR (Watchdog Control) register, which has the following structure:

[WDP2:WDP1:WDP0] – (Watchdog prescaler select) These bits determine the overflow time of the timer as shown in Table 6.10.

Before modifying [WDP2:WDP1:WDP0], it is recommended to disable or reset the watchdog, to avoid accidental activation.

The watchdog is enabled by writing 1 in the WDE (Watchdog Enable) bit. Disabling is more complicated, for safety reasons. An additional control bit WDTOE (Watchdog Turn-Off Enable) has been introduced Prior to clearing WDE, WDTOE and WDE must be both set to 1 in the same operation, and, in the next four cycles, WDE can be written with 0.

WD_DISABLE:

LDI R16,$1F ;WDTOE=1,WDE=1

LDI R17,$17 ;WDTOE=1,WDE=0

OUT WDCTR,R16

OUT WDCTR,R17

RET

To clear the watchdog counter, and reset the watchdog, the special instruction WDR (Watchdog Reset) has been provided.

94 7 Interfacing to Analog Signals

The inputs of the comparator are connected to pins PB2, PB3 of the circuit. The corresponding lines of port B must be configured as inputs, with the internal pull-up resistors disabled (refer to Chap. 2 for details).

The Control and Status Register ACSR

The bits in the Control and Status Register (ACSR) of the comparator offer the following control features:

•Control of the comparator’s power supply, by means of the ACD (Analog Comparator Disable) bit. Setting this bit to 1 disables the comparator.

•Read the status of the comparator’s output in the ACO (Analog Comparator Output) bit.

•Select the event that triggers the interrupt mechanism by using the [ACIS1:ACIS0] control bits (Analog Comparator Interrupt Mode Select). The event selected by these bits sets the ACI flag (Analog Comparator Interrupt flag), which may generate an interrupt request. Refer to Table 7.1 for a description of how the events that set the ACI flag are related to the bits ACIS1:ACIS0.

•If the ACIC (Analog Comparator Input Capture Enable) control bit is set, the output of the comparator ACO is directly connected to the control logic that selects the input capture event for Timer1. In this case, the settings described in Chap. 6 for the selection of the capture edge apply.

The configuration of the bits in the ACSR control and status register is as follows:

The ACI interrupt flag is erased by writing 1 in this position of the ACSR register, or by hardware, when the interrupt is executed.

Table 7.1. The effect of programming [ACIS1:ACIS0]

Example: Consider the following sequence of instructions:

LDI R16,$88

OUT ACSR,R16

Fig. 7.3. Block diagram of a typical ADC

the SAR (Successive Approximation Register), a DAC (Digital to Analog Converter), and an analog comparator.

The conversion result is delivered in an ADC data register, along with an End of Conversion Flag in the ADC status register. Optionally, the End of Conversion Flag can generate an interrupt.

7.4 The A/D Converter of the HC11 Family of Microcontrollers

The HC11 A/D converter has the following characteristics:

•8-bit resolution.

•128 clock periods conversion time.

•Separate AVDD and AGND supply pins, to reduce the effect of noise.

•The entire A/D conversion system power supply is software controllable using the ADPU (Analog to Digital Converter Power Up) bit from the OPTION register.

•Separate reference voltage inputs VRH and VRL to define the margins of the input voltage domain. An input voltage equal to VRL is converted to $00, and an input voltage equal to VRH is converted to $FF (full scale).

•The conversion clock can be either the system clock E, or an internal clock generated by a distinct internal oscillator. The selection of the clock is made by means of the CSEL bit in the OPTION register. However, the use of the internal oscillator is recommended only when the frequency of the E clock is below 750 kHz.

•Four conversions are performed in each conversion cycle, either by converting four times the same input, or by converting four different inputs. The selection between the single-channel mode and multiple-channel mode is done using the MULT control bit from the ADCTL control register.

•There are four registers to store the conversion results named ADR1–ADR4

(A/D Result Registers). When the converter operates in single-channel mode (MULT = 0), the four ADR registers store the results of the four consecutive

conversions performed on the selected channel. When the converter operates in multiple-channel mode (MULT = 1), each of the four ADR registers contains the converted value of a different input from the selected input group.

•The ADC can operate either under software control, when a conversion is started by writing to the ADCTL register, or in continuous mode, when, after finishing a conversion cycle, a new cycle is automatically restarted. To select the continuous conversion mode, set the SCAN control bit to 1.

•There is no interrupt associated with the A/D converter for HC11. This event is marked only by setting the CCF (Conversion Complete Flag) status bit in the ADCTL register.

The control and status bits related to the A/D converter are distributed in OPTION and ADCTL register as follows:

The OPTION Register

•ADPU – A/D Power-Up. At RESET, ADPU is cleared, therefore it is required to set this bit to 1 by software, to enable the A/D subsystem. Note that, after power-up, the converter needs a settle time of about 10 ms.

•CSEL – AD clock select.

CSEL = 0 selects the system clock E as the A/D clock.

CSEL = 1 selects a clock supplied by an internal RC internal oscillator.

The other bits in the OPTION register refer to other subsystems or functions of the microcontroller, and will not be discussed here.

The ADCTL Register

•CCF – Conversion Complete Flag. This read only bit is automatically erased

when writing to the ADCTL which is tantamount to a start conversion command, and is automatically set at the end of a four conversion cycle. When SCAN = 1, CCF is set at the end of the first cycle of four conversions.

•SCAN – Continuous Scan Control bit.

SCAN = 0 single conversion cycle. SCAN = 1 continuous scan.

•MULT – Multiple-channel/single-channel control.

MULT = 0 the conversions are made on a single-input channel, selected by the

[CD:CC:CB:CA] bits

MULT = 1 the conversions are executed on a four-channel group. In this case, the CB and CA selection bits have no effect and the conversions are performed on the four input group addressed by the CD:CC

•[CD:CC:CB:CA]-channel select. The CD bit is reserved for factory testing – always use CD = 0. The effect of the other three bits is described in Table 7.2.

7.5 Exercises on Programming the A/D Converter of HC11

SX 7.1

Write the initialization sequence that prepares the A/D subsystem to be used with the E clock, in single-channel conversion mode, single conversion cycle.

Solution

At RESET, the APDU bit from the OPTION register is cleared. The initialization sequence must set ADPU to 1 to power up the converter. The E clock is selected by erasing the CSEL bit. These initializations must be made after RESET, at least 10 ms before the first conversion cycle. For the other initializations: erasing the MULT bit to select the single-channel operating mode, and SCAN for single conversion cycle, can be made directly in the start conversion routine.

The required initialization routine is this:

SX 7.2

Write a subroutine that receives as input in A the address of the analog channel. The subroutine starts the conversion of the specified channel, waits for the end of conversion and returns the conversion result in A.

Solution

The conversion is automatically started by any write operation to the ADCTL register. CCF = 1 indicates the end of the conversion. When SCAN = 0, four consecutive conversions are performed on the same analog input. At the end of conversion, the four result registers ADR1–ADR4 contain the results of the four conversions. Here is the subroutine that performs the requested operations:

SX 7.3

Write a subroutine that starts the conversion and reads the AN4–AN7 channels, updating the variables ANALOG4–ANALOG7.

Solution

To execute a conversion cycle on a group of four inputs, the bit MULT in ADCTL must be set to 1. The inputs AN4–AN7 are selected by CC = 1 (when MULT = 1, CB and CA are ignored). The required control word for ADCTL is 00010100 = $14. To read the group AN0–AN3, the control word would be $10. The subroutine performing the requested tasks looks like this:

*MASTER SPI initialization routine

100 7 Interfacing to Analog Signals

STAA ANALOG6

LDAA ADR4

STAA ANALOG7

RTS

7.6 The A/D Converter of the AVR Microcontrollers

The AVR ADC has some distinguishing features, compared to HC11:

•10-bit resolution. Therefore, the conversion result is presented in two registers (ADCH:ADCL).

•The ADC can generate an interrupt request at the end of conversion.

•The ADC can operate while the CPU is in sleep mode. This reduces the errors caused by noise.

•A dedicated prescaler generates the ADC clock.

•The ADC can operate in two different modes: single conversion and free running.

When in free running operating mode the ADC works like the HC11 ADC with SCAN = 1. In single conversion mode, only the selected channel is converted, then the ADC halts until a new conversion is started by software.

Details on the Implementation of the ADC of AT90S8535

The control and status register of the A/D Converter, ADCSR, has the following structure:

•ADEN – AD Converter Enable. When ADEN = 1 the ADC is enabled. This bit is cleared at RESET, therefore it is required to set it to 1 in the initialization sequence.

•ADSC – A/D Start Conversion Command. Writing 1 to this bit starts the conversion. Once written with 1, the bit remains set until the end of the conversion. Writing 0 to this bit has no effect.

•ADFR – A/D Free Running Mode select. When set, this bit selects the free running operating mode. In this mode, the ADC permanently samples the input line and executes conversions.

•ADIF – A/D Interrupt Flag. This bit is set automatically at the end of a con-

version after the data registers have been updated. If the ADC interrupts are enabled (ADIE = 1) ADIF = 1 generates an interrupt request. ADIF is automatically cleared when executing the interrupt service routine, or by writing 1 in the corresponding position of ADCSR.

•ADIE – AD Interrupt Enable. When set to 1, this bit enables the interrupts from the ADC subsystem. The interrupt is generated at the end of the conversion, by the ADIF flag.