Appendix E: VHDL Reserved Words
From VHDL 87: |
ENTITY |
OPEN |
WAIT |
|
EXIT |
OR |
WHEN |
ABS |
FILE |
OTHERS |
WHILE |
ACCESS |
FOR |
OUT |
WITH |
AFTER |
FUNCTION |
PACKAGE |
XOR |
ALIAS |
GENERATE |
PORT |
|
ALL |
GENERIC |
PROCEDURE |
From VHDL 93: |
AND |
GUARDED |
PROCESS |
|
ARCHITECTURE |
IF |
RANGE |
GROUP |
ARRAY |
IN |
RECORD |
IMPURE |
ASSERT |
INOUT |
REGISTER |
INERTIAL |
ATTRIBUTE |
IS |
REM |
LITERAL |
BEGIN |
LABEL |
REPORT |
POSTPONED |
BLOCK |
LIBRARY |
RETURN |
PURE |
BODY |
LINKAGE |
SELECT |
REJECT |
BUFFER |
LOOP |
SEVERITY |
ROL |
BUS |
MAP |
SIGNAL |
ROR |
CASE |
MOD |
SUBTYPE |
SHARED |
COMPONENT |
NAND |
THEN |
SLA |
CONFIGURATION |
NEW |
TO |
SLL |
CONSTANT |
NEXT |
TRANSPORT |
SRA |
DISCONNECT |
NOR |
TYPE |
SRL |
DOWNTO |
NOT |
UNITS |
UNAFFECTED |
ELSE |
NULL |
UNTIL |
XNOR |
ELSIF |
OF |
USE |
|
END |
ON |
VARIABLE |
|
|
|
|
|
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Bibliography
Armstrong J. R. and F. G. Gray, VHDL Design Representation and Synthesis, Englewood Cli¤s, NJ: Prentice Hall, 2nd Edition, 2000.
Bhasker J., VHDL Primer, Englewood Cli¤s, NJ: Prentice Hall, 3rd Edition, 1999.
Chang K. C., Digital Systems Design with VHDL and Synthesis—An Integrated Approach, Los Alamitos, CA: IEEE Computer Society Press, 1999.
Hamblen J. and M. Furman, Rapid Prototyping of Digital Systems, Boston: Kluwer Academic Publisher, 2nd Edition, 2001.
Naylor D. and S. Jones, VHDL: A Logic Synthesis Approach, London: Chapman & Hall, 1997. Navabi Z., VHDL Analysis and Modeling of Digital Systems, New York: McGraw-Hill, 1993. Pellerin D. and D. Taylor, VHDL Made Easy, Englewood Cli¤s, NJ: Prentice Hall, 1997. Perry D. L., VHDL, New York: McGraw-Hill, 2nd Edition, 1994.
Yalamanchili S., Introductory VHDL from Simulation to Synthesis, Englewood Cli¤s, NJ: Prentice Hall, 2001.
Yalamanchili S., VHDL Starter’s Guide, Englewood Cli¤s, NJ: Prentice Hall, 1998.
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