Periodicals: Advertiser Supported Trade Magazines

INDEX

8031 microcontroller, 125–126

8051 microcontroller: address modes, 52–55 architecture, 28–30

bit addressable memory, 37–38 control unit, 33

data memory, 35–36

direct and register addressing, 43–46 generic address modes, 51–52 hardware, 32–41

immediate addressing, 5051 indirect addressing, 46–50 input/output ports, 38 instruction register, 33 instruction set, 42–43 internal data memory, 34–35

internal program memory, 33–34 memory organization, 30–32 oscillator and timing circuitry, 41–42 program counter, 33

register banks, 38 reset circuitry, 39–41 serial input/output, 38 timer/counter, 38

A

address bus, 25

address decoder, 121, 153–155 address map, 122–124 address space, 120

analog to digital converter (ADC), 180 anti-fuses, 148

application specific integrated circuit (ASIC):

defined, 145

field programmable gate array (FPGA), 146

full custom, 145 gate arrays, 146 standard cell, 145

arbitration, 177

229

architectures: Harvard, 4–5, 24

microcontroller, 4–6, 24 von Neumann, 4, 24

B

bank switching, 118 benchmarks, 207

bit addressable memory, 37–38 block parity, 112

burst mode, 177 bus:

address, 25 bandwidth, 119 control, 25 data, 24–25

multiplexed, 20–21

C

cache memory, 114

central processing unit (CPU): address bus, 118

address map, 122–124 address spaces, 120 bank switching, 118 control bus, 119

data bus, 119

read and write operations, 117–118 checksum, 112

clock frequency, 62–63 confidence checks, 111–112 construction methods, 197–198 control bus, 25

counters, 179

critical code segments, 187–188 cyclic redundancy code (CRC), 113

D

Darlington transistor, 167 data bus, 25–25

design considerations:

battery powered systems, 205

230EMBEDDED CONTROLLER

Hardware Design

device selection, 207–208 thermal analysis, 204 timing analysis, 127–133

development tools: hardware, 201–202 programmable logic device

(PLD), 155–157 software, 203

device selection criteria, 207–208 digital to analog converter (DAC), 180 diodes, 9

direct access memory, 99–100 direct CPU input/output

interfacing, 161–162 direct memory access (DMA):

burst mode, 177 cycle stealing, 177 defined, 176

electromagnetic compatibility (EMC), 199 electrostatic discharge (ESD), 199–200 erasable programmable read-only memory

(EPROM), 102–103

error detection and correction: block parity, 112 checksum, 112–113 confidence checks, 111

cyclic redundancy code (CRC), 113 defined, 111

error sources, 111 Hamming code, 112 hard errors, 111 horizontal parity, 112 soft errors, 111 vertical parity, 112

event-driven subroutine calls, 184–185 external data memory cycles:

memory read, 134–136 memory write, 136–138

F

fan-out and loading analysis, 63–70 fault tolerance, 200–201

flash erasable programmable read-only memory (EPROM), 103

fuse-link programmable logic device (PLD), 147

fuse map, 147

G

ground bounce, 72–75 ground plane, 198 ground problems, 198

H

Hamming code, 112 hard errors, 111

hardware development tools, 201–202 Harvard architecture, 4–5

horizontal parity, 112

I input/output:

direct CPU interfacing, 161–162

direct memory access (DMA), 176–178 level conversion, 180

matrix display devices, 171–173 matrix keyboard input, 170–171 output current limitations, 166–170 parallel ports, 178

program-controlled I/O bus interfacing, 173–175

power relays, 181

port for the 8051 family, 162–166 serial ports, 179

universal asynchronous receivertransmitter (UART), 179

instruction decoder, 33 interfacing, TTL to CMOS, 78–82 interrupt cycles, 184

interrupt driven program elements, 186 interrupt service routine (ISR), 185 interrupts:

cycles, 184

edge triggered, 190

event-driven subroutine call, 184–185 hardware, 183, 184–185

keyboard, 185 level triggered, 190 maskable, 189 non-maskable, 190

non-vectored, 193–194

parallel interrupt prioritization, 194–195 processing options, 189–190

program elements, 186

serial interrupt prioritization, 194

231 INDEX

software, 183, 184 vectored, 192–193

J

Joint Electronic Device Engineering Committee (JEDEC) standard, 105–106

L

level conversion, 180

level triggered interrupts, 190 logic families:

CMOS, 77–78 NMOS, 77 Schottky, 77 TTL, 75–77

logic symbols, 17–19

M

maskable interrupts, 189 matrix display devices, 172–173 matrix keyboard, 170–171 memory:

asynchronous, 110 bit addressable, 37–38 cache, 114

direct access, 99–100

dynamic random access (DRAM), 100 electrically erasable programmable

read-only, 103

erasable programmable read-only (EPROM), 102–103

flash erasable programmable read-only (EPROM), 103

mask read-only, 101

non-volatile random access (NVRAM), 104–105

organization considerations, 107–108 primary, 96–97

programmable (PROM), 101–102 random access (RAM), 98 read-only, 101–104

read/write, 100–101 secondary, 96–97 sequential access, 98

static random access (SRAM), 100 synchronous, 110

timing considerations, 109–110

virtual, 114–115 volatility, 98

memory-mapped input/output, 121 memory organization, 107–108 memory read, 26

memory write, 26 multiplexed bus, 20–21

N

noise margin analysis, 82–90 non-maskable interrupts, 190 non-vectored interrupts, 193–194 non-volatile random access memory

(NVRAM), 104–105

O

Ohm’s law, 8

P

parallel interrupt prioritization,194–195 parallel ports, 178

partial address coding, 123 power, 8

power plane, 198 power relays, 181 primary memory, 96–97

printed circuit board (PCB), 197 prioritization schemes, 189, 194–195 processor performance metrics, 206 program-controlled I/O bus interfacing,

173–175

programmable array logic (PAL), 146, 151– 153

programmable logic array (PLA), 146, 151 programmable logic devices (PLDs):

anti-fuses, 148 architectures, 148–150 assembler, 155 compiler, 155 defined, 146

designing using personal computers, 157–158

development tools, 155–157 fuse-link, 147

input/output decoding using, 157 programmable read-only memory

(PROM) as, 150

232EMBEDDED CONTROLLER

Hardware Design

sum-of-products logic, 147 test vectors, 156

Verilog, 156

VHDL, 156

programmable read-only memory (PROM), 101–102

programmable read-only memory (PROM) programmer, 106–107

propagation delays, 59–60 pulse width, 62

R

random access memory (RAM): defined, 98

dynamic (DRAM), 100 non-volatile (NVRAM), 104–105 static (SRAM), 100

read-only memory (ROM): defined, 101

erasable programmable (EPROM), 102–103

mask, 101

programmable (PROM), 101–102 read and write operations, 117–118 real-time processing, 175 re-entrant code, ‘86

reset circuitry, 39–41 resistance, 7–9

rise and fall times, 59

S

secondary memory, 96–97 semaphores, 188–189 sequential access memory, 99

serial interrupt prioritization, 194 serial ports, 179

setup and hold times, 60–61 single cycle direct memory access

(DMA), 177 soft errors, 111

software development cycle, 55 software development tools, 55–56, 203 special function register (SFR), 31 static random access memory

(SRAM), 100 sum-of-products logic, 147

switches: mechanical, 10 transistor, 11–17

T

test instruments, 202–203 test vectors, 156–157 thermal analysis, 204 timers, 179

timing analysis: preliminary, 127–133

worst case, 90–92 timing diagrams: defined, 19–20

notation conventions, 58–59 transistors:

CMOS, 14–15

Darlington, 167 FET, 12–13 NMOS, 13

operation, 9–10 switches, 11–17

transmission line effects, 70–72 tri-state bus interfacing, 61–62 tri-state logic, 18–19

U

universal asynchronous receiver-transmitter (UART), 179

V

vectored interrupts, 192–193 Verilog, 156

vertical parity, 112 VHDL, 156

virtual memory, 114–115 voltage, 7

von Neumann architecture, 4

W

wiring capacitance, 66–68 worst-case design, 57

worst-case timing analysis, 90–92

Z

zero-insertion force (ZIF) socket, 107