90EMBEDDED CONTROLLER
Hardware Design
This voltage is maintained while sourcing the LSTTL IIH max of 60 A.
Solving for Rmax :
Rmax <= 1.6 V / 60 A = 26.7 kilohms maximum
Thus, the acceptable range for the pull up resistor is
1.62 kilohms <= RPU <= 26.7 kilohms
An acceptable standard value such as 10 kilohms would be appropriate.
Another limit relates to the rise time of the signal under load, due to the R-C time constant of the pull-up resistor charging the load capacitance, CL. From the example above, let’s see what the effect of this time constant is on the selection of the resistor value.
The maximum R value can be approximated by the equation:
R = T / CL where T is the rise time and CL is the total load capacitance
Ignoring the Ioh current of the LSTTL driver, if the circuit above had an allow able rise time T = 50 nS and CL = 20 pF, then the maximum R value would be:
Rmax = 50 nS / 20 pF = 2.5 kilohms maximum to maintain the 50 nS rise time.
So a better choice might be a standard 2.2 kilohm pull-up resistor. Since the driver will supply some current to charge the load capacitance, this is a fairly conservative value. We would also have to allow for the additional rise time as part of the timing analysis for the low-to-high transition.
Worst-Case Timing Analysis Example
Let’s suppose an LSTTL gate is used to enable the D input of a flip-flop frequency divider, as shown in Figure 3-16. Figure 3-17 shows a
functional timing diagram for the circuit in |
IN |
D Q |
||
|
||||
Figure 3-16, and Figure 3-18 illustrates a specifi |
Clock |
|
> CK |
|
cation timing diagram for the same circuit. The |
|
|||
|
||||
|
|
|
||
timing of the input signals must conform to the |
Figure 3-16: Example of |
|||
combined specs of both devices, as defined below: |
||||
worst-case timing. |
|
|||
91CHAPTER THREE
Worst-Case Timing, Loading, Analysis, and Design
Clock
IN 
D
Q
Figure 3-17: Functional timing diagram for Figure 3-16.
Clock
Q
IN
D
|
|
|
|
|
|
overall |
|
|
|
|
|
|
TSU |
TPCKQ TPLH |
|
|
||||
TSU |
||||||
|
or |
for |
||||
TPLH FF
Figure 3-18: Specification timing diagram for Figure 3-16.
Flip-Flop Timing Specs
Symbol |
min |
typ |
max |
units |
|
|
|
|
|
TSU |
10 |
|
|
nS |
TH |
1 |
|
|
nS |
TPCKQ |
|
|
15 |
nS |
TPWCK |
10 |
|
|
nS |
FCLK |
|
|
50 |
MHz |
Gate Timing Specs
Symbol |
min |
typ |
max |
units |
|
|
|
|
|
TPHL |
1 |
2 |
5 |
nS |
TPLH |
2 |
4 |
6 |
nS |
Test conditions RL = 1K, CL = 100 pF
For the circuit shown in Figure 3-16 and the accompanying specifications, what is the maximum guaranteed clock rate?