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Hardware Design Checklist

DC and AC loading can be summarized in a spreadsheet as shown below:

5. Verify Worst Case Timing Conditions

All timing specifications should be evaluated for potential timing violations, as covered in chapter 6. This is particularly important for signals that are heavily loaded requiring de-rating of the timing specs, or tri-state signals that are subject to bus contention problems.

6. Determine if Transmission Line Termination is Required

The signal rise time and maximum trace length must be evaluated to deter­ mine if a signal interconnect must be treated as a transmission line, requiring constant impedance along the length of the trace, and termination to prevent reflections. If the signal has a fast rise time and trace length, L, greater than about one-sixth the edge length of the pulse, then it is necessary to analyze the circuit as a transmission line using this formula:

L = Tr / D where

L = length of rising or falling edge in inches (in)

Tr = rise time in picoseconds (pS)

D = delay in picoseconds per inch (pS/in)

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For traces on a standard printed circuit board, the value for D will be in the range of 100 to 200 pS/in. Depending upon how much distortion you’re willing to live with, the critical trace length will be between one-sixth and one-quarter of the length of a trace corresponding to the signal’s transition. For a trace that is shorter than one-sixth the length of the signal’s rising or falling edge, the circuit seldom needs to be considered to be a transmission line. Traces that are much longer than one-quarter the length of the fastest edge will start to behave as transmission lines, exhibiting reflections of the signal when the transition gets to the far end of the trace and is reflected back to the near end. Once the trace is about half of the length it takes for a logic transition to propagate, the problems become quite pronounced.

7. Clock Distribution

Distribution of clock signals must be done in a way that compromises the need to minimize clock skew, while avoiding reflections that can cause unac­ ceptable clock transitions due to transmission line effects. Distributing clocks in such a way as to avoid excessive skew implies the use of a clock tree to provide equal time delay to each load. However, a tree topology is in direct conflict with the need to maintain a single, stubless transmission line. The ideal transmission line is essentially “daisy-chained” with a trace that has constant impedance across its length and has no stubs, but that usually results in maxi­ mum timing skew! Clock signals should also be isolated from other signals to prevent crosstalk between the clock and other signals. Clock signals should generally NOT be gated, to avoid undesirable side effects.

8. Power and Ground Distribution

Ground and power planes are recommended on printed circuits wherever possible, because they allow low impedance connections and provide high frequency decoupling from inter-plane capacitance. Ground connections should be as short as possible, especially for ground pins on multiple output logic devices, to prevent ground bounce.

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Hardware Design Checklist

Capacitors for Bypassing Power Supply Noise

The power and ground pins of every IC should be bypassed using a capacitor with low impedance at the frequencies of interest (determined by rise time, not clock rate). The self-resonance of larger capacitors, such as 0.1 microfarad, may result in little effect on the fast current transients present in high-speed logic chips. 0.01 or 0.001microfarad (or even hundreds of picofarads) low inductance capacitors, are more appropriate for fast logic devices having sub-5 nanon­ second rise times. Multi-layer ceramic dielectric surface mount capacitors work better than leaded, tantalum or electrolytic capacitors at high frequencies. Each board in a system should also have a larger tantalum or electrolytic capacitor to provide medium frequency bypassing for peak currents.

When possible, power supply and ground connections should be made independently to the power supply, to minimize common impedances, also known as ground loops. This is especially important for circuits containing mixed analog and digital circuitry.

Mixed Analog and Digital Circuitry

The analog power supply should be separately regulated from the digital supply, to provide a quiet power source to the analog circuitry. Separate power and ground planes should be maintained to minimize coupling between noisy digital circuits and sensitive analog or RF (radio frequency) circuits. Analog power planes should not overlap with digital planes, as the digital noise will couple through the inter-plane capacitance. Digital and analog grounds should only be interconnected at one point, usually very near the analogdigital conversion IC.

High impedance analog signals should be physically and electrically isolated from digital signals to minimize digital noise on the analog signals.

Digital inputs that are driven by analog circuitry should be clamped, using a series resistor and low forward voltage Schottky diodes, to power and ground to clamp the signals to levels that are within the logic input specification levels.

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Safety

High voltage conductors should be physically and electrically isolated from low level and user accessible signals to avoid potential shock hazards. All conductors should be sized large enough to allow carrying maximum current, under short circuit conditions, and protective devices, such as fuses and PTC switches, should be used to prevent. Conductors carrying more than 40 volts and telephone line conductors must be isolated by at least onequarter inch from other conductors or transformer isolated for safety agency and telecom approvals.

9. Asynchronous Inputs

Asynchronous inputs should be synchronized using two levels of flip-flops to minimize the probability of a metastable state when asynchronous inputs are sampled. This is particularly important for programmable logic devices, which may have slow recovery times from metastable states.

10. Guarantee Power-On Reset State

Verify that any devices, such as CPU, PLDs, and registers, are reset to a known state when power is applied, or whenever power falls below normal operating levels (brown out condition). All CPUs, counters, registers, shift registers and memory devices are subject to unpredictable behavior when the power is out of spec and must be reset after the power returns to specified levels.

11. Programmable Logic Devices

Verify that all flip-flops in the device will be in a known state upon power-up, and that any counters and state machines with unused states will transition to a valid state in the event that they get into an invalid state.

Leave a few available input and output pins available to facilitate changes in the event that additional logic functions become necessary.