Hardware

Design Checklist

A complete and reliable design requires all of the innumerable details to be evaluated and analyzed correctly. The following checklist is intended to provide a guide for the designer to ensure that all the important design aspects have been evaluated. This up-front effort is a significant effort, but is less expensive and time consuming than searching for the errors once a design has been committed to production.

Schematics are an essential part of any hardware design review. To facilitate the review, here are a few general guidelines that should be followed during preparation of the schematics for a project:

•Multi-page schematics should be structured hierarchically.

•A top level sheet should be created showing the interconnects between other sheets.

•In each drawing, all inputs should on the left side and a;;outputs on the right side of the page.

Detailed Checklist

This checklist can be used as the basis of a technical design review, or in evaluating the correctness of hardware designs produced by others.

List all integrated circuits used in the design, along with the required supply voltage and percentage tolerance or range of voltages, and the actual power supply voltage range that will be encountered by these devices. Some CAD systems will assist with this process, but they may be more trouble to use than the effort warrants. Most of these analyses can be documented and calculated using a simple spreadsheet.

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Hardware Design

1. Define Power Supply Requirements

All power supply voltages and tolerances should be listed, along with the typical and maximum current requirements over the temperature range for each device. A crtitical and highly reliable design should leave significant margin (50 to 100% excess capacity) between required load and maximum available supply current, reducing the stress on the power supply. This is particularly important, since heavy loading on a power supply increases the temperature of the power handling components, significantly reducing the long term reliability of the power supply. Power supplies are among the devices in a system which are the most likely to fail, and often take other components with them when they do.

From this data, the power supply requirements would be:

•Vdd = Vcc = 5 volts +/-5% 150 milliamperes minimum plus 100 milliam­ peres margin becomes 5 volts 5% at 250 milliamperes.

•Vref =2.5 V +/-1% 10 milliamperes minimum derived from +5 V supply using a 5 V reference IC.

•–5 V 5% 100 milliamperes minimum plus 50 milliamperes margin becomes

–5V 5% at 150 milliamperes.

•+12V 10% 100 milliamperes minimum plus 50 millamperes margin becomes +12V 10% at 150 milliamperes.

Verify that the voltages delivered to all the devices are within their specifica­ tions, and that the sum of the worst case currents used by the devices can be supplied by the power source with some margin.

When a prototype circuit is available, measure actual power consumption to verify that it is within expected limits. The current consumption of subse­ quent units can be compared to a known good device.

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Hardware Design Checklist

2. Verify Voltage Level Compatibility

The voltage levels that will occur at the interface to each type of chip that is in the design must be compatible. This must be evaluated for two purposes: so that the correct output logic level is interpreted by the driven input, and to avoid potential damage to device inputs. The ability of the device to tolerate input voltages without damage is usually defined as an absolute maximum rating and the normal operating logic levels are defined in a section that is usually called DC characteristics. An example of the maximum levels is the Vih maximum spec, which defines the maximum input voltage that an input can withstand without potentially damaging the device’s input. A 3 volt gate might have Vcc+0.3 volt maximum input specification, and driving it with the output of a 5 volt logic gate can damage the 3V gate input.

A key element of voltage level compatibility is noise margin analysis. Look at the Voh-Vih and Vil-Vol logic levels on all parts that interconnect to determine if sufficient noise margins are available. The hard part is determining just what an acceptable noise margin is for a given device. Several issues must be considered, including the anticipated noise environment and the required reliability level. Clearly it would be prudent to insure a high level of noise immunity designing with large noise margins for a cardiac pacemaker design! A hand-held game would not warrant the same level of reliability and result­ ing expense. If there is TTL compatible logic in a system, it probably doesn’t make sense to design for a noise margin in excess of the inherent 400 milli­ volts level inherent in the TTL specs. When evaluating the noise margin of devices such as a microcontroller and an memory, it’s fairly common to find that the memory’s specs result in a noise margin of 200 millivolts or less, as shown in the example below:

Noise Margin Analysis - Example

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Hardware Design

Since many systems employ logic using different power supply voltages, such as mixed 5 and 3.3 volt logic, it is important to verify that the signals that cross the boundary have sufficient noise margins, and do not exceed the maximum input voltage ratings. In some cases, level conversion or voltage clamping circuits may be necessary. Some 3 volt logic devices are tolerant of 5 volt signal levels on some of their input pins, simplifying the design. On the other hand, 3 volt CMOS outputs can often drive 5 volt logic with TTL compatible inputs directly.

3. Check DC Fan-Out: Output Current Drive vs. Loading

Maximum logic output currents (IOL and IOH) are specified, usually at a specific output voltage (VOL and VOH respectively) . The total load current that an output drives must be compared to the inputs and any resistors the output must drive, and sufficient margin must be allowed to guarantee proper operation.

Some logic outputs, such as IRQ and DMA request lines, frequently use opendrain or open-collector buses, which require pull-up resistors. Open-drain or open-collector outputs must be identified and pulled up with an appropriate resistor. Unused inputs should be pulled to their inactive state: either pulled up to the supply through a resistor, or connected to ground, as appropriate.

Pull-up resistor values must be chosen to minimize the rise time using as small a value as will satisfy the maximum IOL of the weakest open-drain device driving the line.

4. AC (Capacitive) Output Drive vs. Capacitive Load and De-rating

Device timing is usually specified under specific loading conditions on the outputs. If the actual capacitive load on the outputs, consisting of the driven logic inputs and stray wiring capacitance, exceeds the load capacitor specified in the output device’s timing test conditions, then the timing specs will not be valid. If the amount of overload is not severe, it is possible to estimate the additional delay required to charge the excess capacitance. The delay depends upon the available charging current and actual load capacitance.