- •Objectives
- •Embedded Microcomputer Applications
- •Microcomputer and Microcontroller Architectures
- •Digital Hardware Concepts
- •Voltage, Current, and Resistance
- •Diodes
- •Transistors
- •Mechanical Switches
- •Transistor Switch ON
- •Transistor Switch OFF
- •The FET as a Logic Switch
- •NMOS Logic
- •CMOS Logic
- •Mixed MOS
- •Logic Symbols
- •Tri-State Logic
- •Timing Diagrams
- •Multiplexed Bus
- •Loading and Noise Margin Analysis
- •The Design and Development Process
- •Chapter One Problems
- •2 Microcontroller Concepts
- •Organization: von Neumann vs. Harvard
- •Microprocessor/Microcontroller Basics
- •Microcontroller CPU, Memory, and I/O
- •Design Methodology
- •Introduction to the 8051 Architecture
- •Memory Organization
- •CPU Hardware
- •Oscillator and Timing Circuitry
- •The 8051 Microcontroller Instruction Set Summary
- •Direct and Register Addressing
- •Indirect Addressing
- •Immediate Addressing
- •Generic Address Modes and Instruction Formats
- •Address Modes
- •The Software Development Cycle
- •Software Development Tools
- •Chapter Two Problems
- •Timing Diagram Notation Conventions
- •Rise and Fall Times
- •Propagation Delays
- •Setup and Hold Time
- •Tri-State Bus Interfacing
- •Pulse Width and Clock Frequency
- •Fan-Out and Loading Analysis—DC and AC
- •Calculating Wiring Capacitance
- •Fan-Out When CMOS Drives LSTTL
- •Transmission Line Effects
- •Ground Bounce
- •Logic Family IC Characteristics and Interfacing
- •Interfacing TTL Compatible Signals to 5 Volt CMOS
- •Design Example: Noise Margin Analysis Spreadsheet
- •Worst-Case Timing Analysis Example
- •Chapter Three Review Problems
- •Memory Taxonomy
- •Secondary Memory
- •Sequential Access Memory
- •Direct Access Memory
- •Read/Write Memories
- •Read-Only Memory
- •Other Memory Types
- •JEDEC Memory Pin-Outs
- •Device Programmers
- •Memory Organization Considerations
- •Parametric Considerations
- •Asynchronous vs. Synchronous Memory
- •Error Detection and Correction
- •Error Sources
- •Confidence Checks
- •Memory Management
- •Cache Memory
- •Virtual Memory
- •CPU Control Lines for Memory Interfacing
- •Chapter Four Problems
- •Read and Write Operations
- •Address, Data, and Control Buses
- •Address Spaces and Decoding
- •Address Map
- •Chapter Five Problems
- •The Central Processing Unit (CPU)
- •External Data Memory Cycles
- •External Memory Data Memory Read
- •External Data Memory Write
- •Design Problem 1
- •Design Problem 2
- •Design Problem 3
- •Completing the Analysis
- •Chapter Six Problems
- •Memory Selection and Interfacing
- •Preliminary Timing Analysis
- •Introduction to Programmable Logic
- •Technologies: Fuse-Link, EPROM, EEPROM, and RAM Storage
- •PROM as PLD
- •Programmable Logic Arrays
- •PAL-Style PLDs
- •Design Examples
- •PLD Development Tools
- •Simple I/O Decoding and Interfacing Using PLDs
- •IC Design Using PCs
- •Chapter Seven Problems
- •Direct CPU I/O Interfacing
- •Port I/O for the 8051 Family
- •Output Current Limitations
- •Simple Input/Output Devices
- •Matrix Keyboard Input
- •Program-Controlled I/O Bus Interfacing
- •Real-Time Processing
- •Direct Memory Access (DMA)
- •Burst vs. Single Cycle DMA
- •Cycle Stealing
- •Elementary I/O Devices and Applications
- •Timing and Level Conversion Considerations
- •Level Conversion
- •Power Relays
- •Chapter Eight Problems
- •Interrupt Cycles
- •Software Interrupts
- •Hardware Interrupts
- •Interrupt Driven Program Elements
- •Critical Code Segments
- •Semaphores
- •Interrupt Processing Options
- •Level and Edge Triggered Interrupts
- •Vectored Interrupts
- •Non-Vectored Interrupts
- •Serial Interrupt Prioritization
- •Parallel Interrupt Prioritization
- •Construction Methods
- •10 Other Useful Stuff
- •Electromagnetic Compatibility
- •Electrostatic Discharge Effects
- •Fault Tolerance
- •Software Development Tools
- •Other Specialized Design Considerations
- •Thermal Analysis and Design
- •Battery Powered System Design Considerations
- •Processor Performance Metrics
- •Device Selection Process
- •Power and Ground Planes
- •Ground Problems
- •11 Other Interfaces
- •Analog Signal Conversion
- •Special Proprietary Synchronous Serial Interfaces
- •Unconventional Use of DRAM for Low Cost Data Storage
- •Digital Signal Processing / Digital Audio Recording
- •Detailed Checklist
- •Define Power Supply Requirements
- •Verify Voltage Level Compatibility
- •Check DC Fan-Out: Output Current Drive vs. Loading
- •Verify Worst Case Timing Conditions
- •Determine if Transmission Line Termination is Required
- •Clock Distribution
- •Power and Ground Distribution
- •Asynchronous Inputs
- •Guarantee Power-On Reset State
- •Programmable Logic Devices
- •Deactivate Interrupt and Other Requests on Power-Up
- •Electromagnetic Compatibility Issues
- •Manufacturing and Test Issues
- •Books
- •Web and FTP Sites
- •Periodicals: Subscription
- •Periodicals: Advertiser Supported Trade Magazines
- •Programming Microcontrollers in C, Second Edition
- •Controlling the World with Your PC
- •The Forrest Mims Engineers Notebook
- •The Forrest Mims Circuit Scrapbook, Volumes I and II
- •The Integrated Circuit Hobbyist’s Handbook
- •Simple, Low-Cost Electronics Projects
178EMBEDDED CONTROLLER
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the memory, at a reduced bandwidth. As a result, the CPU may be a bit slower because it will sometimes have to wait for a DMA cycle to complete, but it is not entirely shut out when a DMA transfer is in progress. When a single cycle DMA transfer occurs, more time is used in acquiring and transferring control of the memory to and from the DMA controller since it happens so much more fre quently. This “overhead” frequently reduces the overall available memory band width, especially when it is performed sequentially with the data transfers. Some systems overlap the memory bus arbitration handshaking with the memory data transfers so that the arbitration does not slow down the data transfers.
Direct memory access is required when the CPU is too slow to transfer the data under program control. Because the CPU does not have to participate directly in the item-by-item transfer of data, DMA is also useful when there are other tasks that the CPU can perform. In those cases, DMA transfers may be used even though they are not strictly required by the data rate.
Elementary I/O Devices and Applications
Parallel ports are the simplest form of I/O, but there are many different types of electrical interfaces ranging from the simple open collector TTL outputs used on a PC printer port to high-speed peripheral interfaces such as the IEEE-488 and SCSI buses. Most embedded controller ICs have some pins that are config urable as parallel input or output. These interfaces are appropriate for simple I/O, such as key switch and display interfacing. They are also appropriate for controlling and monitoring high-level interfaces such as solid-state relays.
The parallel I/O ports available on the 8051 family and similar processors are fairly versatile, with special internal circuitry to allow a port bit to be config ured individually as an input or output. Some microcontrollers also provide considerable current source and sink capability, however the 8051 family parts are usually fairly weak in that regard.
Serial ports, also referred to as asynchronous or synchronous communications (COM) interfaces, are commonly used to interconnect with devices, such as modems, which inherently transmit the data one bit at a time over a commu nication link such as a phone line. The RS-232 serial interface used in a PC’s COM port is an asynchronous serial data stream. An asynchronous interface
179CHAPTER EIGHT
Basic I/O Interfaces
has no explicit clock signal to synchronize the transfer of data. The timing of bits is based on the absolute bit rate, and is synchronized on every character with a start bit. The serial to parallel conversion is performed by a UART (universal asynchronous receiver-transmitter). When transmitting data, the UART appends a start bit before the data, shifts out the data LSB first, and adds a stop bit after the data. Once the transmission is complete, the UART sets a status bit indicating that the data has been sent and that it is ready to begin transmission of another character.
When receiving data, the UART looks for and synchronizes to the leading edge of a start bit. Then, it delays for one and one-half of a bit period, so that it samples the LSB in the middle of the bit period. Then, the UART delays one bit period, samples the next to the LSB, etc. until all the bits have been shifted in. Once all the data has been received, it is loaded into a buffer register and a status bit is set to indicate that the receive buffer contains a character and may be read by the CPU. In order for this method to work, the two UARTS at each end of the communication must have bit rate clocks that are accurate enough to guarantee that the data will be sampled at the right time. This typically requires a sample clock that is 16 times the data rate, accurate to 1% to 2%.
Timers and counters, which are present in most microcontroller chips, allow generation of pulses and interrupts at regular intervals. They can also be used to count pulses and measure event timing. Some of the more sophisticated versions can measure frequency, pulse width, and relative pulse timing on inputs. Outputs can be defined to have a given repetition rate, pulse width, and even complex sequences of pulses in some cases. In most cases, one of the timers can be used to generate the necessary serial clocks required to operate a microcontroller’s on-chip UART. In order to meet the approximately1% clock frequency accuracy for the 16x data rate clocks, the crystal frequency is often chosen to allow exact integer division of the crystal frequency resulting in an accurate, standard serial data rate. This is why 8051 family parts that use their internal counters and serial port to connect to standard 9600 bps and higher data rates use the crystal frequency 11.059 MHz rather than an even 12 MHz.
Analog to digital converters (ADCs) and digital to analog converters (DACs) are used to convert continuously variable real world parameters to digital form and back to analog. Examples include conversion of the output voltage of a temperature sensor into digital form for processing, and converting control
180EMBEDDED CONTROLLER
Hardware Design
values back into analog form to adjust the temperature. Most of the quantities of interest in the real world tend to be continuous and analog in nature, so these converters are critical for many applications.
Timing and Level Conversion Considerations
Depending upon the rate and load on the processor, peripherals can be inter faced using interrupt driven, program controlled, or DMA I/O. High speed devices will generally require DMA, while devices that generate small amounts of data at unpredictable times are better handled with interrupts and program controlled I/O.
Level Conversion
Many types of devices that need to be interfaced to the processor are not compatible with standard logic levels. For example, many serial interfaces comply with an interface standard, such as the EIA RS-232 specification, which defines the voltage level and pin out. RS-232 levels are nominally plus and minus 12 volts, instead of the 0 to 5 volt levels that most processors use. As a result, level shifting devices are needed to translate between the 0 to5 and +/-12 volt signals. Single ICs that provide the translation as well as gener ating the +/-12 volt supplies from a single +5 volt supply, are now available (Maxim MAX232 and others), making this much easier for embedded system designers.
Intermediate DC voltages can often be handled using simple open-collector outputs, or a separate transistor and pull up resistor to drive output voltages higher than the logic supply. Power switching FETs are also available that can handle relatively high currents and voltages, and can be driven directly by logic-level outputs.
Power Relays
High-level outputs, such as 110 volt AC loads, must be switched using solid state or magnetic relays. The magnetic relay windings are inductive coils that must be clamped using a diode to prevent large inductive transients from