- •Objectives
- •Embedded Microcomputer Applications
- •Microcomputer and Microcontroller Architectures
- •Digital Hardware Concepts
- •Voltage, Current, and Resistance
- •Diodes
- •Transistors
- •Mechanical Switches
- •Transistor Switch ON
- •Transistor Switch OFF
- •The FET as a Logic Switch
- •NMOS Logic
- •CMOS Logic
- •Mixed MOS
- •Logic Symbols
- •Tri-State Logic
- •Timing Diagrams
- •Multiplexed Bus
- •Loading and Noise Margin Analysis
- •The Design and Development Process
- •Chapter One Problems
- •2 Microcontroller Concepts
- •Organization: von Neumann vs. Harvard
- •Microprocessor/Microcontroller Basics
- •Microcontroller CPU, Memory, and I/O
- •Design Methodology
- •Introduction to the 8051 Architecture
- •Memory Organization
- •CPU Hardware
- •Oscillator and Timing Circuitry
- •The 8051 Microcontroller Instruction Set Summary
- •Direct and Register Addressing
- •Indirect Addressing
- •Immediate Addressing
- •Generic Address Modes and Instruction Formats
- •Address Modes
- •The Software Development Cycle
- •Software Development Tools
- •Chapter Two Problems
- •Timing Diagram Notation Conventions
- •Rise and Fall Times
- •Propagation Delays
- •Setup and Hold Time
- •Tri-State Bus Interfacing
- •Pulse Width and Clock Frequency
- •Fan-Out and Loading Analysis—DC and AC
- •Calculating Wiring Capacitance
- •Fan-Out When CMOS Drives LSTTL
- •Transmission Line Effects
- •Ground Bounce
- •Logic Family IC Characteristics and Interfacing
- •Interfacing TTL Compatible Signals to 5 Volt CMOS
- •Design Example: Noise Margin Analysis Spreadsheet
- •Worst-Case Timing Analysis Example
- •Chapter Three Review Problems
- •Memory Taxonomy
- •Secondary Memory
- •Sequential Access Memory
- •Direct Access Memory
- •Read/Write Memories
- •Read-Only Memory
- •Other Memory Types
- •JEDEC Memory Pin-Outs
- •Device Programmers
- •Memory Organization Considerations
- •Parametric Considerations
- •Asynchronous vs. Synchronous Memory
- •Error Detection and Correction
- •Error Sources
- •Confidence Checks
- •Memory Management
- •Cache Memory
- •Virtual Memory
- •CPU Control Lines for Memory Interfacing
- •Chapter Four Problems
- •Read and Write Operations
- •Address, Data, and Control Buses
- •Address Spaces and Decoding
- •Address Map
- •Chapter Five Problems
- •The Central Processing Unit (CPU)
- •External Data Memory Cycles
- •External Memory Data Memory Read
- •External Data Memory Write
- •Design Problem 1
- •Design Problem 2
- •Design Problem 3
- •Completing the Analysis
- •Chapter Six Problems
- •Memory Selection and Interfacing
- •Preliminary Timing Analysis
- •Introduction to Programmable Logic
- •Technologies: Fuse-Link, EPROM, EEPROM, and RAM Storage
- •PROM as PLD
- •Programmable Logic Arrays
- •PAL-Style PLDs
- •Design Examples
- •PLD Development Tools
- •Simple I/O Decoding and Interfacing Using PLDs
- •IC Design Using PCs
- •Chapter Seven Problems
- •Direct CPU I/O Interfacing
- •Port I/O for the 8051 Family
- •Output Current Limitations
- •Simple Input/Output Devices
- •Matrix Keyboard Input
- •Program-Controlled I/O Bus Interfacing
- •Real-Time Processing
- •Direct Memory Access (DMA)
- •Burst vs. Single Cycle DMA
- •Cycle Stealing
- •Elementary I/O Devices and Applications
- •Timing and Level Conversion Considerations
- •Level Conversion
- •Power Relays
- •Chapter Eight Problems
- •Interrupt Cycles
- •Software Interrupts
- •Hardware Interrupts
- •Interrupt Driven Program Elements
- •Critical Code Segments
- •Semaphores
- •Interrupt Processing Options
- •Level and Edge Triggered Interrupts
- •Vectored Interrupts
- •Non-Vectored Interrupts
- •Serial Interrupt Prioritization
- •Parallel Interrupt Prioritization
- •Construction Methods
- •10 Other Useful Stuff
- •Electromagnetic Compatibility
- •Electrostatic Discharge Effects
- •Fault Tolerance
- •Software Development Tools
- •Other Specialized Design Considerations
- •Thermal Analysis and Design
- •Battery Powered System Design Considerations
- •Processor Performance Metrics
- •Device Selection Process
- •Power and Ground Planes
- •Ground Problems
- •11 Other Interfaces
- •Analog Signal Conversion
- •Special Proprietary Synchronous Serial Interfaces
- •Unconventional Use of DRAM for Low Cost Data Storage
- •Digital Signal Processing / Digital Audio Recording
- •Detailed Checklist
- •Define Power Supply Requirements
- •Verify Voltage Level Compatibility
- •Check DC Fan-Out: Output Current Drive vs. Loading
- •Verify Worst Case Timing Conditions
- •Determine if Transmission Line Termination is Required
- •Clock Distribution
- •Power and Ground Distribution
- •Asynchronous Inputs
- •Guarantee Power-On Reset State
- •Programmable Logic Devices
- •Deactivate Interrupt and Other Requests on Power-Up
- •Electromagnetic Compatibility Issues
- •Manufacturing and Test Issues
- •Books
- •Web and FTP Sites
- •Periodicals: Subscription
- •Periodicals: Advertiser Supported Trade Magazines
- •Programming Microcontrollers in C, Second Edition
- •Controlling the World with Your PC
- •The Forrest Mims Engineers Notebook
- •The Forrest Mims Circuit Scrapbook, Volumes I and II
- •The Integrated Circuit Hobbyist’s Handbook
- •Simple, Low-Cost Electronics Projects
138EMBEDDED CONTROLLER
Hardware Design
We’ll now look at three typical design problems and show how to use the techniques described in this chapter to solve them.
Design Problem 1
For the same three paths in Figure 6-3, find the maximum allowable clock rate, given the slowest EPROM from Table 6-2. Use the specs for the -30 part which has a 300 nS access time and the same address latch specs in Table 6-3. Consider the 8031, EPROM, and 74ALS373 latch specs as discussed in the sections describing Paths A, B and C.
Solution: In this case, we are given the component timing, and we need to solve for the minimum clock period (T = 1/maximum clock frequency).
Path A:
The CPU allows TAVIV = 5*T-100 nS
The EPROM uses Taa = 300 nS
The limiting condition is TAVIV = Taa, so:
5T-100 = 300
5T = 400 T = 80 nS
Path B:
The CPU allows TAVIV = 5*T-100 nS
The EPROM uses Taa = 300 nS
The latch uses TPHL D->Q = 16 nS
The limiting condition is Taa + Tlatch = TAVIV, so:
TAVIV = Taa + Tplatch and TAVIV = 5T-100, so:
5T-100 = 300 + 16
5T = 416 T = 83 nS
Path C:
The limiting condition is TPLIV = Toe of the EPROM, so:
The EPROM Toe from the table is 120 nS
The equation is TPLIV = Toe
139CHAPTER SIX
A Detailed Design Example
Solving for T, we have:
3T - 100 = 120
3T = 220
T = 220/3 = 73 nS
Of all three paths, the longest period is due to Path B at 83nS, so it is the limit to the clock rate for the specs considered here.
Paths A and C are not constraints for this case.
So Path B is the limiting case when /OE is connected to /PSEN, and the maxi mum clock frequency is 1/83nS = 12 MHz.
Note that Path B is just at the spec limit for 12 MHz operation (1/83 nS = 12 MHz), so the maximum clock is 12 MHz, even for a faster EPROM.
Also notice that if /PSEN was instead connected to /CE, (Path C), the TPLIV spec would be the limiting factor: TPLIV = 3T-100 = Tce of the EPROM. The EPROM Tce from the table is 300 nS. Solving for T, we have:
3T-100 = 300
3T = 400
T = 400/3 = 133 nS.
For this case, 1/133 nS = 7.5 MHz would be the maximum allowable clock rate.
Design Problem 2
You have an existing processor design, and you need to define what the mini mum acceptable specs are for the program EPROM to determine which vendors and part numbers will work in the system. Assuming a clock rate of 12 MHz for the 8051, determine the following specs for the memory chip to be used with it, assuming the same address latch used in the previous examples, and find the maximum acceptable values for:
•Tce max (chip enable acess time)
•Taa max (address access time)
•Tod max (output disable time, referred to as Tdf in the EPROM spec)
Assume /PSEN is connected to the EPROM /CE and EPROM /OE is grounded.