124EMBEDDED CONTROLLER

Hardware Design

Note also that two separate address ranges have been used, one for the input port and one for the output port. In practice, it is possible to have the input and output ports respond to the same address by using the read line for input cycles, and the write line for outputs.

Table 5-2: External data memory map (8031 external memory space).

The decoder will select the input port at any address in the range E000 through FFFF hex. That means that the single input port bit takes up 8K address loca­ tions, all reading the same input port. This decoding technique is partial address decoding because only the three most significant address bits are decoded for this input port, and the rest of the address lines are effectively “don’t cares.” This may seem wasteful of address space, but it reduces the amount of decoding circuitry when it is not necessary to decode all the unique addresses individually. The memory map of the external data memory address space is shown in Table 5-2.

Chapter Five Problems

1.If the design of Figure 5-7 needs to be changed to eliminate the duplication of addresses caused by partial address decoding, how many additional input signals would be required for the decoder?

2.The 8031 CPU has 16 address lines. How much external memory can be attached to it without resorting to any memory extension mechanism?

3.If all bits of Port 1 on an 8031 are used to select external data memory in one of 256 “banks,” what is the maximum amount of external data memory that can be accessed?

4.What is the answer to life, the universe, and everything?

A Detailed

Design Example

In this chapter, we will take a detailed look at the design and analysis of a simple microcontroller project. This chapter will illustrate the interactive nature of the design process. First, the preliminary design is analyzed for limitations and violations of the timing requirements for the various chips. Then modifications and additions to the design are made to improve the performance based on the analysis. The modified design is then verified for conformance to the various component specifications. This iterative process begins with a simple block diagram showing the components of interest and progresses to detailed timing diagrams, specifications, and timing analysis.

The Central Processing Unit (CPU)

The process of designing an embedded microcomputer system is mostly independent of the particular CPU that is used. The example design of this chapter is a relatively simple one that illustrates the design and analysis process in enough detail to show what needs to be done. Because the Intel 8031 microcontroller design has a simple bus interface, has brief timing specifications, uses SRAM, and incorporates relatively simple I/O on chip, it will be used to illustrate the critical design and analysis processes. Once the complete process is understood with this simple CPU, more advanced designs can be addressed with comparative ease.

The 8031 processor is a Harvard architecture with a multiplexed address and data bus. There are three address spaces: internal RAM, external data RAM, and external program ROM. The external program ROM and data RAM are