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As soon as the address latch enable (ALE) is high, the address latch allows the multiplexed address from the address/data bus through to the latch output. When the ALE signal goes low, the address remains frozen on the latch output, and the CPU can remove the address lines from the bus and begin a data transfer.

The address latch must be a transparent latch with active high enable, such as the 74xx373 device. Figure 5-4 shows a typical arrangement. It is important to recognize that a transparent latch operates differently than a clocked register. As long as the ‘373 latch enable input is high, the latch Q output follows the D input. As soon as the latch enable goes inactive, the latch Q outputs freeze. This is analogous to the way a VCR allows a continuously changing signal show on the display until the pause button is pushed. This is in contrast with edge sensitive devices, such as the ‘374, which only updates the Q outputs at the rising edge of the clock. The ‘374 is analogous to a flash still camera, which

to access the addressed location.

Address Spaces and Decoding

Processors, depending upon the particular architecture, may have several separate address spaces, such as the following:

•program memory address space

•data memory address space

•input/output device address space

•stack address space

Depending on the processor, these may be completely separate, overlapping, or all-in-one address space. When these are separate spaces, the processor has separate control signals to indicate which address space is to be used for data transfer. This may be done with a separate signal line that goes active when a particular space is being addressed, such as a program fetch denoting that the

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data should be transferred from a program memory address. The address space selection may also be performed using several status lines that, when decoded, define the appropriate transfer as in the case of the Intel 80x86 family. When there are separate address spaces, as in Harvard architecture CPUs like the 8051 family, there will be more than one unique location with

the same address. The status and control lines are needed to single out the appropriate location as shown in Figure 5-5.

that have separate I/O instructions and address space may have some memory mapped I/O by dedicating some of the memory address space to I/O devices.

The various address lines and control lines are decoded to provide individual chip select signals for the various memories and I/O chips. This is the purpose of the address decoder. A standard n-line to 2n-line decoder is sometimes used to decode the address lines. A typical device is the 74LS138, a 3-to-8 line decoder that drives one of eight output lines low, depending on the three bit binary number on the input. For

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the address bus and each of the eight decoder outputs to a memory IC chip enable, one of the eight memory devices will be selected for any given ad­ dress. Decoders also have enable inputs that can be used to enable the outputs only for a selected address space such as memory or I/O. The example in Figure 5-6 shows an 8031 with eight program EPROMs.

Address Map

In order to describe the address decoding of memory and I/O clearly an address map (also referred to as a memory map) table is used to specify which devices respond to a particular range of addresses in a given address space. The purpose of an address map is to clearly define the range of addresses that each memory or I/O device occupies in the address space. A separate map is used for each address space in processors that have more than one address space. For example, the 8031 has a factory defined map of the internal data memory address space, another map for program memory, and a third for external data memory. It also helps to define which memory space any given device resides in. As an example, the address decoding table for Figure 5-6 is shown in Table 5-1:

Table 5-1: Memory map for Figure 5-6.

The same decoding technique can be applied to I/O devices to select one of several devices. In the case of an I/O decoder connected to a processor with a separate I/O address space, the decoder’s enable input would be controlled by the CPU I/O control line. Whenever an I/O cycle occurs, the I/O device address is presented on the address bus and the I/O control line is activated. This causes one of the decoder outputs to go active and select an input or output port. In

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the case of memory mapped I/O, the decoder outputs would go to both memory and I/O devices. An I/O address map is used to specify the location(s) in I/O address space that each device will respond to. The map may also specify if the location is read only, write only, or read/write. This is because I/O device addresses are not always read and write. As an example, an output port that drives some LEDs would be an output only or “write only” port. Microcon­ troller chips usually have some dedicated input bits and output bits as well as some general purpose I/O port bits implemented directly on the chip, which are usually accessible by reading or writing special register addresses. Micro­ processors and microcontrollers with external buses can also have memory mapped I/O. The example below shows a one bit input port and a 1-bit output port mapped into the external RAM space along with six 8Kx8 RAMs.

The example address map in Table 5-1 and decoder circuit in Figure 5-6 illustrate complete address decoding. That is, there is one device mapped to each block of addresses in such a way that all the addresses map to one and only one unique set of memory locations. Each of the eight memories containing eight kilobytes of memory maps to one of the eight regions of eight kilobytes. There are no unused addresses, and there are no duplications. If all possible addresses are decoded, but some are not used, then it is possible to expand the memory available by using the available memory address ranges for additional memory. If any device is decoded in such a way that it appears more than once in the address space, then it is referred to as partial address decoding. This derives from the fact that not all the address signals are used to determine which device should be enabled. This is often done to reduce the complexity of the decod­ ing circuits, at the