92EMBEDDED CONTROLLER

Hardware Design

From the timing figures on the previous page, note the minimum clock cycle time is defined by the sum of the following times: the time it takes for the transition from the active edge of the clock for the signal at D to propagate through the flip-flop, through the NAND gate and the time the signal must be stable before the next clock. The maximum propagation times and minimum setup times are used as they are the most severe requirements.

f = 1/t = 1/31nS = 32.26 MHz

Now let’s determine the setup and hold time requirements for the overall circuit. The overall setup time is lengthened by the delay of the NAND gate, therefore the system setup time is the sum of the flip flop setup time and the worst case propagation delay.

TSU(system) = TPLH + TSU(flip-flop) = 16 nS minimum

For the overall system hold time, the hold time of the flip-flop is offset by the minimum delay through the NAND gate, as this is the minimum amount of time that can be counted on to delay a changing D input to the flip-flop.

TH(system) = TH(flip-flop) - TPHL(min) = 1 - 1 = 0 nS

The delay in the D signal path reduced the hold time requirement from 1 nS to 0 nS, meaning the input can change at the same time as the clock edge or later. This is actually an improvement on the performance of the flip-flop by itself, which requires that the D line be held stable for 1 nS after the clock edge.

Chapter Three Review Problems

For the following problems, refer to the loading example and Figure 3-15.

1.If a 10 kilohm pull-up resistor is used, how many additional LSTTL loads can be connected?

2.How many CMOS loads could be added?

3.What could be done to increase the number of LSTTL loads?

93CHAPTER THREE

Worst-Case Timing, Loading, Analysis, and Design

For the following problems, refer to the timing example and Figure 3-16.

1.Using the same D flip-flop specified in the example, how fast could it be clocked if the /Q output was directly connected to the D input? (That is, eliminating the gate from the circuit.)

2.Under what conditions would the addition of a pull-up or pull-down resistor increase the fan-out of a logic output?

3.What, if anything, can be done to increase fan-out when it is limited by AC (capacitive) loading?

4.A 32-bit CMOS 5 volt microprocessor that has a 32-bit address bus and a separate 32-bit data bus, and the processor has a 1 nS rise time and 0.5 nH of ground inductance on a board made from glass epoxy material. The processor has output high and low voltages of 4.5 and 0.5 volts respectively and drives a capacitance of 100 pF on the address and data buses. How long can the printed circuit traces be before they must be considered as transmission lines?

5.For the same processor and conditions described in the last problem, what is the worst-case ground bounce voltage that can be expected?

Memory Technologies

and Interfacing

Memory is one of the technology drivers in the integrated circuit business because the highly repetitive nature of memory arrays. Relatively small improvements in the design of a memory bit multiplied by the large number of bits on a chip can make a big difference in chip cost and performance. Gordon Moore, one of the founders of Intel Corporation, stated memory size doubles approximately every two years. The generalized version of Moore’s Law (named after Gordon Moore, a co-founder of Intel who first articulated it) states that chip complexity doubles approximately every two years. As can be seen from Figure 4-1, as the resolution of features is reduced by a factor of 1/n, the area required

for a gate is reduced by 1/n2. This exponential growth in complexity

has continued in spite of those who have pointed out many reasons why it cannot

continue. The sup­ posed barriers have

been overcome so far by various means to compensate for the limits of basic physics,

such as pre-distorting the master patterns to compensate for optical diffraction effects.