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Another common form of conversion, used for digital signals, is logic level conversion. This is required for serial I/O devices conforming to the RS-232 standard, which uses logic voltages in the -12 to +12 volt range rather than the lower voltages that are standard on digital processors and logic. There are special level translation ICs which have voltage multipliers and negative voltage generators as well as level converters on a single IC. These devices take a +5 volt supply, convert it to + and -12 volts, and translate to and from standard logic levels. Logic level conversion is also required when interfacing two incompatible logic families, such as TTL and ECL.

Special Proprietary Synchronous Serial Interfaces

Many embedded systems require the use of a few specialized I/O devices, and the limited pin count of a microcontroller chip can make it difficult to interface all the desired I/O. In order to allow I/O expansion without using many of the pins on a microcontroller, several manufacturers have adopted a serial bus mechanism. Some of the devices are unique and proprietary, but there are two that are standardized:

•Philips’ serial bus, trademarked as I2C (for Inter-Integrated Circuit bus)

•National’s serial bus, trademarked as MicroWire

The I2C bus is much more flexible because it allows many devices to coexist on the bus. It is also more complex, as it allows for a large number of device addresses and multiple masters. The MicroWire bus is relatively simple, but requires additional I/O pins for multiple devices.

Unconventional Use of DRAM for Low Cost Data Storage

In some applications, static RAM (SRAM) is too expensive for data storage. A low cost alternative is to use dynamic RAM (DRAM) and handle the address multiplexing and refresh under software control. On a cost-per-bit basis, DRAM is significantly less expensive than SRAM. If the cost of address multiplexing and refresh hardware is added to the DRAM cost, it is not cost effective

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for small memories. In general, interfacing a DRAM directly to a microcontroller under software control is the best way to get extremely low cost-per-bit storage. It’s used for applications like voice storage in low cost digital answering machines. It works well, and there are a lot of tricks you can use, such as refreshing all the rows in one burst. The disadvantage is that a significant amount of processor time has to be used to refresh the memory. In addition, each read or write access has the overhead of multiplexing the address bits and strobing the /RAS and /CAS lines under program control.

In some cases the entire memory is not needed, so it is possible to reduce the number of I/O pins used to interface to the address lines. This would seem to be wasteful, but the price of memory chips must be considered. For current chip designs, larger memories cost more than smaller ones. Once DRAM parts become obsolete, the prices for small, obsolete parts actually become greater than larger memories because the smaller chips are no longer produced in volume. It is possible to use a portion of a larger memory chip by connecting some of the address lines in parallel and ignoring the additional memory. The reason you can’t just fix some of the address lines high or low is that some devices require a changing level on the address lines for internal circuitry that pre-charges the select lines in the array. The locations you can’t access won’t be refreshed, but that won’t matter since they’re not used.

Modern DRAMs have automatic refresh circuits which perform a refresh cycle using /CAS before /RAS refresh cycles, and even include internal refresh address counters. As an example, a 1Mx4 DRAM part provides 512 kilobytes of data four bits at a time. It can be fully refreshed by pulsing /CAS then /RAS low once for every row in the memory array. Having access to four bits at a time reduces the address multiplexing I/O overhead compared to using a 4Mx1 DRAM.

Digital Signal Processing / Digital Audio Recording

A common use for DRAM is in low cost digital voice recording, such as that used in some digital answering machines and toys. A microcontroller could be used in conjunction with a DRAM to record and play back voice. Standard telephone digital voice circuits sample at a rate of 8000 samples per second companded at eight bits per sample, which is 8 kilobytes/second, or 64 kilobits/ second. Telephone circuits have a theoretical 4 kilohertz Nyquist bandwidth

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limit, but a 3 kilohertz practical audio bandwidth due to filter design constraints, which is consistent with the bandwidth of an analog phone system. At 8000 samples per second, it would only be possible to store four seconds of audio in a 32 kilobyte SRAM. Using a 1Mx4 part would allow 512/8 = 64 seconds of speech in one DRAM chip.

Standard telephone CODEC (COder/DECoder) ICs have special logarithmic analog to digital and digital to analog converters as well as low pass anti-aliasing and smoothing filters built in. They’re used in huge quantity in digital telephone equipment. CODECs have serial I/O, but at 64,000 samples per second they’re probably too fast for devices such as a programmable interface controller (PIC). It is also possible to reduce the sample rate if a reduced bandwidth is acceptable.

A four chip system consisting of a microcontroller, a DRAM IC, a CODEC IC, and an audio amplifier IC could be used to store and play back speech at a cost of a few dollars. The length of the recording can be increased using data compression techniques. Special compression algorithms reduce the redundancy inherent in most audio signals, such as voice. There are some very efficient coding schemes such as linear predictive coding (LPC) that have the ability to store compressed speech at rates as low as a few thousand bits per second. They actually model the human vocal tract. The trade off is that the computational load for compression and decompression are fairly large to get high compression ratios. It’s fairly simple to playback and is useful for pre-recorded speech. That’s what is used in many talking toys like Texas Instruments’ “Speak and Spell.” TI developed the LPC algorithm, and was first to sell it in consumer products.

Simpler compression schemes, like adaptive differential pulse code modulation

(ADPCM), can give as much as 4:1 compression ratios without much computation. A compression ratio of 4:1 would result in 2 kilobytes per second of compressed speech. ADPCM encodes differences between samples instead of the raw values. Some applications don’t require high quality audio, so there are quite a few corners that can be cut. For example, it’s possible to reproduce intelligible speech using samples of less than eight bits. Four bits is probably enough for some voice storage applications. It is even possible to reproduce intelligible speech on the one bit digital output of the PC’s speaker! At the other extreme, some signals, such as music, require higher sample rates and more bits per sample. Compact audio discs (standard CDs), for example, use

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44,100 samples per second at 16 bits per channel per sample to store very high quality audio. This results in 44,100 samples/second * 16 bits/sample/ channel * 2 channels = 1,411,200 bits per second of stereo audio. (Actual data rates are slightly higher, in order to accommodate synchronization and other overhead.)