- •Table of Contents
- •Objectives
- •Embedded Microcomputer Applications
- •Microcomputer and Microcontroller Architectures
- •Digital Hardware Concepts
- •Voltage, Current, and Resistance
- •Diodes
- •Transistors
- •Mechanical Switches
- •Transistor Switch ON
- •Transistor Switch OFF
- •The FET as a Logic Switch
- •NMOS Logic
- •CMOS Logic
- •Mixed MOS
- •Real Transistors Don’t Eat Q!
- •Logic Symbols
- •Tri-State Logic
- •Timing Diagrams
- •Multiplexed Bus
- •Loading and Noise Margin Analysis
- •The Design and Development Process
- •Chapter One Problems
- •Organization: von Neumann vs. Harvard
- •Microprocessor/Microcontroller Basics
- •Microcontroller CPU, Memory, and I/O
- •Design Methodology
- •The 8051 Family Microcontroller
- •Processor Architecture
- •Introduction to the 8051 Architecture
- •8051 Memory Organization
- •8051 CPU Hardware
- •Oscillator and Timing Circuitry
- •The 8051 Microcontroller Instruction Set Summary
- •Direct and Register Addressing
- •Indirect Addressing
- •Immediate Addressing
- •Generic Address Modes and Instruction Formats
- •8051 Address Modes
- •The Software Development Cycle
- •Software Development Tools
- •Hardware Development Tools
- •Chapter Two Problems
- •Timing Diagram Notation Conventions
- •Rise and Fall Times
- •Propagation Delays
- •Setup and Hold Time
- •Tri-State Bus Interfacing
- •Pulse Width and Clock Frequency
- •Fan-Out and Loading Analysis—DC and AC
- •Calculating Wiring Capacitance
- •Fan-Out When CMOS Drives LSTTL
- •Transmission Line Effects
- •Ground Bounce
- •Logic Family IC Characteristics and Interfacing
- •Interfacing TTL Compatible Signals to 5 Volt CMOS
- •Design Example: Noise Margin Analysis Spreadsheet
- •Worst-Case Timing Analysis Example
- •Chapter Three Review Problems
- •Memory Taxonomy
- •Secondary Memory
- •Sequential Access Memory
- •Direct Access Memory
- •Read/Write Memories
- •Read-Only Memory
- •Other Memory Types
- •JEDEC Memory Pin-Outs
- •Device Programmers
- •Memory Organization Considerations
- •Parametric Considerations
- •Asynchronous vs. Synchronous Memory
- •Error Detection and Correction
- •Error Sources
- •Confidence Checks
- •Memory Management
- •Cache Memory
- •Virtual Memory
- •CPU Control Lines for Memory Interfacing
- •Chapter Four Problems
- •Read and Write Operations
- •Address, Data, and Control Buses
- •Address Spaces and Decoding
- •Address Map
- •Chapter Five Problems
- •The Central Processing Unit (CPU)
- •Memory Selection and Interfacing
- •Preliminary Timing Analysis
- •External Data Memory Cycles
- •External Memory Data Memory Read
- •External Data Memory Write
- •Design Problem 1
- •Design Problem 2
- •Design Problem 3
- •Completing the Analysis
- •Chapter Six Problems
- •Introduction to Programmable Logic
- •Technologies: Fuse-Link, EPROM, EEPROM, and RAM Storage
- •PROM as PLD
- •Programmable Logic Arrays
- •PAL-Style PLDs
- •Design Examples
- •PLD Development Tools
- •Simple I/O Decoding and Interfacing Using PLDs
- •IC Design Using PCs
- •Chapter Seven Problems
- •Direct CPU I/O Interfacing
- •Port I/O for the 8051 Family
- •Output Current Limitations
- •Simple Input/Output Devices
- •Matrix Keyboard Input
- •Program-Controlled I/O Bus Interfacing
- •Real-Time Processing
- •Direct Memory Access (DMA)
- •Burst vs. Single Cycle DMA
- •Cycle Stealing
- •Elementary I/O Devices and Applications
- •Timing and Level Conversion Considerations
- •Level Conversion
- •Power Relays
- •Chapter Eight Problems
- •Interrupt Cycles
- •Software Interrupts
- •Hardware Interrupts
- •Interrupt Driven Program Elements
- •Critical Code Segments
- •Semaphores
- •Interrupt Processing Options
- •Level and Edge Triggered Interrupts
- •Vectored Interrupts
- •Non-Vectored Interrupts
- •Serial Interrupt Prioritization
- •Parallel Interrupt Prioritization
- •Construction Methods
- •Power and Ground Planes
- •Ground Problems
- •Electromagnetic Compatibility
- •Electrostatic Discharge Effects
- •Fault Tolerance
- •Hardware Development Tools
- •Instrumentation Issues
- •Software Development Tools
- •Other Specialized Design Considerations
- •Thermal Analysis and Design
- •Battery Powered System Design Considerations
- •Processor Performance Metrics
- •Benchmarks
- •Device Selection Process
- •Analog Signal Conversion
- •Special Proprietary Synchronous Serial Interfaces
- •Unconventional Use of DRAM for Low Cost Data Storage
- •Digital Signal Processing / Digital Audio Recording
- •Detailed Checklist
- •1. Define Power Supply Requirements
- •2. Verify Voltage Level Compatibility
- •3. Check DC Fan-Out: Output Current Drive vs. Loading
- •4. AC (Capacitive) Output Drive vs. Capacitive Load and De-rating
- •5. Verify Worst Case Timing Conditions
- •6. Determine if Transmission Line Termination is Required
- •7. Clock Distribution
- •8. Power and Ground Distribution
- •9. Asynchronous Inputs
- •10. Guarantee Power-On Reset State
- •11. Programmable Logic Devices
- •12. Deactivate Interrupt and Other Requests on Power-Up
- •13. Electromagnetic Compatibility Issues
- •14. Manufacturing and Test Issues
- •Books
- •Web and FTP Sites
- •Periodicals: Subscription
- •Periodicals: Advertiser Supported Trade Magazines
- •Index
173CHAPTER EIGHT
Basic I/O Interfaces
characters to four rows of 40 characters. Graphic display versions of these modules are also available, allowing flexible text and graphic display formats.
Another method of driving small glass displays directly is through special LCD display driver chips, which are designed to drive a relatively simple display (such as one containing simple 7-segment numeric digits, for example). These peripherals are available from several vendors, and the LCD display peripheral driver hardware is even incorporated in some microcontrollers.
Many other types of I/O can be added externally using the processor’s bus interface. The 82C55 chip is a commonly used parallel interface with two 8-bit ports and two 4-bit ports which can be programmed as inputs or outputs. Connecting an 82C55 to the 8051 bus using memory mapping is an example of a program controlled I/O interface.
Program-Controlled I/O Bus Interfacing
In this form of I/O, the processor communicates with I/O devices in essentially the same way it communicates with memory. The program running in the CPU must check the availability of data and transfer it, one piece at a time. The processor puts an I/O address on the bus, indicates the type of transfer, either read or write (I/O read or I/O write cycle for processors with an I/O address space). The CPU uses activates its control lines, and then transfers the data to or from the selected I/O device. The 8051 does not have an external I/O space, so these devices must be mapped into the external data memory address space. Processors with a separate I/O address space, such as the x86 family, have input and output instructions that cause the CPU to generate the appropriate I/O read and I/O write instructions respectively. Processors with a single address space, such as the 68000 family, have no I/O instructions. They use memory mapped I/O, so both software and hardware treat the I/O addresses in the same way as memory.
An I/O interface connects the actual I/O device, such as an LED, a switch or a printer, to the CPU. The job of the designer is to design an interface that meets the requirements of both the I/O device and the bus. While memory devices only read or write data, I/O devices may perform other operations as well. A typical I/O interface has several addresses, usually referred to as I/O ports or I/O registers, for different types of information such as data, commands, and
174EMBEDDED CONTROLLER
Hardware Design
status. These registers are the “window” through which the programs must monitor, control, and communicate with the corresponding I/O device. Three types of information are typically exchanged through this window: commands from the CPU to control the I/O device, status of the I/O device to the CPU, and the actual data to be transferred. Many interfaces have I/O registers corresponding to these three types of information as follows:
•Command Register. This is sometimes referred to as the control register. This register is written by the CPU to control things such as the operating mode of the I/O device, direction of data transfer, enabling or disabling the use of parity, interrupts, and so on. Usually each bit or field of bits is used to control a specific function, but the commands may also be encoded in a way equivalent to that used for encoding information in the CPU instruction op codes. Several of these “control words” may be required to initiate I/O operations. Control words written to the command register would be instructions to the I/O interface on how to perform a specific type of transfer. In some cases the command register is “write-only,” meaning that the information that is written into this register cannot be read back by the CPU.
•Status Register. This register indicates the state of the I/O device at the time the register is read. The bits in this register typically indicate things such as the availability of data to be input as from a keyboard, or output as to a printer. By reading the status register, the program running in the CPU can determine when to transfer data and the presence of errors, among other things. Typical status bits would be “input data ready,” or “output data register full.” Sometimes the status register is “read-only,” meaning that the information in this register can only be controlled by the I/O interface and cannot be written to or modified by the CPU.
•Data Register. This register contains the actual data to be transferred to or from the I/O device. In some cases two separate registers and I/O addresses are used for input and output data, but in most cases they share the same address. Reading or writing information to this register will generally affect one or more status bits indicating the availability of data for the CPU or the I/O device. For example, when the I/O device has data ready for input, it would set the “input data ready” bit of the status register, and when the CPU reads the data register, the “input data ready” bit would be reset.
The process of testing a ready status bit is referred to as polling the device to see if it is ready for data transfer. Before any data can be transferred, the status