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Hardware Design
The output on the printer from the two processes would be intermixed, even though each process appears to have exclusive access, from the data available to each process. The problem occurs because there are two copies of the flag. The sequence of instructions 1 through 4 cannot be interrupted without the potential of improper operation. Such a sequence is referred to as a critical code segment that cannot be interrupted without risk of producing incorrect actions.
Semaphores
One way to fix the critical code segment problem in the preceding paragraph problem would be to disable interrupts before instruction 1, and re-enable them after instruction 4. While this will solve the problem, this solution adds to interrupt latency. A more efficient solution is the use of a semaphore instead of a simple binary flag. A semaphore is a multiple state variable that can be tested and set in one operation (the test and set operation cannot be interrupted). Here is an example of using a semaphore:
Process A |
Process B |
Start: |
Start: |
INC flag; |
INC flag; |
look for FF => 0 change |
look for FF => 0 change |
if result non-zero |
if result non-zero |
then DEC flag |
then DEC flag |
go to Start |
go to Start |
else |
else |
if result = 0 then |
if result = 0 then |
Use Printer |
Use Printer |
... |
... |
Use Printer: |
Use Printer: |
(access the printer) |
(access the printer) |
DEC flag |
DEC flag |
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printer semaphore: >= 0 printer in use
= FF hex, printer not in use
Note that the INC instruction has the ability to test and set the semaphore in one instruction. The semaphore is incremented and the status flags are set in the same instruction. Since an interrupt can only occur between instructions, there is only one instance when the semaphore variable makes the FF to zero transition. If other processes increment the semaphore they will increment
189CHAPTER NINE
Other Interfaces and Bus Cycles
from zero to one or more. The first process that increments the variable from FF hex to zero gets exclusive access to the printer. This is guaranteed because the test and set operation is an indivisible operation, which is the key characteristic of the protection mechanism of a semaphore. It is important to note that increments and decrements must be paired. The semaphore is more powerful than a flag because the processes can all share the printer resource under this scheme. Only the first process using a resource locks out all others. The first process seeing the FF to 0 transition gets the resource.
The 8051 only has one instruction that performs the necessary indivisible test and set operation, the “decrement and jump if not zero” or DJNZ. Most processors have instructions that can be used for the semaphore test and set operation.
Interrupt Processing Options
There are a number of variations in the way interrupts can be handled by the processor. These variations include how multiple interrupts are handled, if they can be turned off, and how they are triggered. Some processors allow multiple (nested) interrupts, meaning the CPU can handle multiple interrupts simultaneously. In other words, interrupts can interrupt interrupts. When multiple interrupts are sent to the CPU, some method must be used to determine which is handled first. Here are the most common prioritization schemes currently in use.
•Fixed (static) multi-level priority. This uses a priority encoder to assign priorities, with the highest priority interrupt processed first. This is the most common method of assigning priorities to interrupts.
•Variable (dynamic) multi-level priority. One problem with fixed priority is that one type of event can “dominate” the CPU to the exclusion of other events. The solution is to rotate priority each time an event occurs. This ensures that no interrupt gets “locked out” and all interrupts will eventually be processed. This scheme is good for multi-user systems because eventually everyone gets priority.
•Equal single-level priority. If an interrupt occurs with an interrupt, the new interrupt gains control of the processor.
Some types of interrupts can be turned on or off under program control. Maskable interrupts are those that can be enabled and disabled by the CPU. These are used for non-catastrophic events, such as a key being pressed. In
190EMBEDDED CONTROLLER
Hardware Design
contrast, non-maskable interrupts (NMI) cannot be enabled for disabled by the CPU. These are reserved for catastrophic events such as a power failure or parity error. Non-maskable interrupts are usually edge triggered (see next section) because we want to “remember” the event before it goes away.
Level and Edge Triggered Interrupts
An interrupt can be level or edge triggered. A level interrupt depends on the logic value, or level, when the interrupt signal is sampled by the CPU at the end of an instruction execution cycle. In contrast, an edge triggered interrupt occurs when a change, or edge transition, occurs in the sampled interrupt signal.
In level triggered interrupts, the interrupt request input signal is sampled by the CPU at the end of each instruction execution, as shown in Figure 9-3.
CPU
Instruction Fetch Execute Fetch Execute Fetch Execute
Activity
IRQ
Interrupt Request Sampling Times
Figure 9-3: CPU sampling of level sensitive interrupt.
In this type of interrupt the IRQ line is sampled by the CPU, so there is a potential problem if the IRQ line goes active and inactive between samples. If the request goes away before it is sampled, the CPU will miss the interrupt. Also, if the interrupt request is still active when the processor has completed processing of the interrupt, it will be called and executed again.
The timing diagram of an edge triggered interrupt is shown in Figure 9-4. When there is an edge on an edge sensitive IRQ, it is latched inside the CPU until it is processed. Figure 9-4 shows an interrupt that is sensitive to falling edges.
CPU
Instruction Fetch Execute Fetch Execute Fetch Execute
Activity
Edge Sensitive IRQ
CPU Internal IRQ
Figure 9-4: Edge sensitive interrupt.
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Other Interfaces and Bus Cycles
It is possible to do the same latching with an external circuit to make a level sensitive interrupt into an edge triggered interrupt by using a flip/ flop to latch the request as shown in Figure 9-5. When IRQ goes high, Q goes high until Clear pulses high, Q goes down.
When IRQ goes high, Q goes high until Clear pulses high, then Q goes down.
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Figure 9-5: Edge to level |
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As a general rule, use edge triggering when the interrupt pulses are very long or very short. Figure 9-6 shows a situation where the request pulses are very long, such as the 60 Hertz square wave that is often used for clock functions. A level sensitive interrupt input would generate multiple interrupts per 60 Hertz cycle. By using an edge sensitive input, there is only one interrupt since there is only one falling edge per cycle. Figure 9-7 shows the opposite situation: very short interrupt pulses. When the pulses are very short, the CPU could miss interrupts as shown below. An edge sensitive input will latch the interrupt until it can be processed.
CPU
Interrupt
Sampling
Clock
Figure 9-6: Long interrupt request cycles require edge sensitive input.
CPU
Interrupt
Sampling
IRQ
Figure 9-7: Short interrupt request pulses require edge sensitive input.
However, there are conditions where level triggering is preferable. When interrupt signals overlap, interrupts may be missed if an edge sensitive interrupt were to be used, as
shown in Figure 9-8. This problem occurs
on a machine where
multiple interrupts are combined on one
request line, as shown