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Hardware Design
that has to respond to, and then process, an event in a fixed amount of time is referred to as a real-time system.
Interrupt Cycles
When a hardware interrupt request is enabled and activated, the CPU saves its current program counter and performs an interrupt cycle in place of the usual program fetch cycle. The interrupt cycle typically consists of the interrupt source identification and the transfer of the interrupt vector information. The interrupt vector is often a pointer to the place in memory where the address of the interrupt service routine is stored. The CPU will then fetch that address and perform what amounts to a subroutine call to that address. When the interrupt subroutine has completed processing of the event that caused the interrupt, the processor executes a “return from interrupt” instruction and goes back to the part of the main program that was executing before the interrupt occurred.
Software Interrupts
A software interrupt is a special subroutine call. It is synchronous meaning that it always occurs at the same time and place in the program that is interrupted. It is frequently used as a quick and simple way to do a subroutine call for accessing programs such as the operating system and I/O programs. A disk operating system used on the PC uses interrupt number 21 (hex) to invoke operating system functions such as reading a disk file, output data to the printer and so on. For the purposes of this chapter, the word “interrupt” by itself will be taken to mean a hardware interrupt.
In Chapter Six, we looked at the 8051 processor’s program read, data read, and data write cycles. However, most processors also have other types of bus cycles, including special cycles for processing hardware interrupts.
Hardware Interrupts
A hardware interrupt can be thought of as hardware induced subroutine call. When an external event—such as the pressing of a key—occurs, an interrupt subroutine is called to store the key code for later use. This type of event-
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driven subroutine call is asynchronous meaning that it can occur at any time and place in the program that is interrupted. Interrupt latency is the term used to describe the amount of time from when an event occurs (such as the pressing of a key) until the interrupt subroutine begins execution.
Among the factors that determine latency are:
•Hardware, which determines the time the CPU requires to process the request and acknowledge sequences (fixed hardware time).
•The time required to get a vector and load it into the processor (“vectored” interrupts will be discussed later in this chapter).
•Sequences of code with interrupts disabled add directly to latency.
•Higher priority interrupts overriding the current interrupt (the time a high priority takes to execute adds directly to the latency of lower priority interrupts). This is reduced by keeping ISRs as short as possible.
Figure 9-1 shows a common hardware interrupt situation— handling a pressed key on
the PC’s keyboard. Figure 9-2 shows the timing sequence for handling the interrupt service routine (ISR) required to process the key press event.
Keyboard: Character“ Ready” |
CPU: |
Interrupt“Requested” |
ControllerInterupt to |
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Figure 9-2: PC |
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keyboard interrupt |
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timing sequence. |
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Input |
Data |
Keyboard |
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Data Ready |
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Port |
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Interrupt Request
Interrupt Acknowledge
Interrupt Vector
Figure 9-1: Keyboard interrupt.
CPU: “OK, What Interrupt No.?” |
CPU: “Interrupt Received” |
Interupt Controller: “Interrupt Request Complete” |
ISR Begins Execution ISR Reads Character and Clears Ready Bit |
Interrupt
Control
Circuit
CPU
Data Ready
Interrupt |
IRQ |
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Request |
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AcknowledgeInterrupt INTAK |
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CPU Bus |
Vector |
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Interrupt to Latency
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Hardware Design
Interrupt Driven Program Elements
When an interrupt is processed, here is a detailed sequence of typical elements involved:
1)Initialization executed once)
a.Disable interrupts (always do this first!).
b.Clear buffers/ pointers/ flags.
c.Store address of ISR(s) in vector table.
d.Initialize interrupt hardware.
e.Clear any interrupt requests.
f.Enable interrupts and enter MAIN routine.
2)Main routine (executed many times, when no interrupts are pending)
a.Performs processes that are not time critical, such as diagnostics.
b.Access any resource that is NOT re-entrant.
c.Wait for interrupts to occur.
3)Interrupt service routine (ISR) executed once per interrupt)
a.Save processor state: registers, flags, interrupt level, etc.
b.Process the event (what we really wanted to do in the first place).
c.Restore processor state: registers, flags, interrupt level, etc.
d.Enable interrupts (may be located at different points in the ISR, depending on requirements).
e.Tell interrupt controller we are finished processing this interrupt return from interrupt.
Re-entrant code or a re-entrant routine is code that can be interrupted at any point when partially complete, then called by another process, and later return to the point where it was interrupted to complete the original function without any errors. Non-re-entrant code, however, cannot be interrupted and then called again without problems. An example of a program that is not re-entrant is one that uses a fixed memory address to store a temporary result. If the program is interrupted while the temporary variable is in use and then the routine is called again, the value in the temporary variable would be changed. When execution returns to the point where it was interrupted, the temporary variable will have the wrong value. In order to be re-entrant, a program must keep a separate copy of all internal variables for each invocation. Re-entrant
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code is required for any subroutines that must be available to more than one interrupt driven task.
Interrupts can be processed between execution of instructions by the CPU any time they are enabled. Most CPUs check for the presence of an interrupt request at the end of every instruction. If interrupts are enabled, the processor saves the contents of the program counter (PC) on the stack, and loads the PC with the address of the ISR. Some CPUs allow certain instructions to be interrupted when they take a long time to process, such as a block move instruction.
Critical Code Segments
Let’s suppose there are two processes that both require occasional use of the printer. In a system that allows a task to be interrupted at any time by another task, simple binary flags will not be reliable. In the example below, two tasks are contending for access to the printer. The flag indicates whether the printer is in use, and is set equal to one to signal other tasks to wait until the printer is available. The premise is that each process will wait until the printer is free before attempting to print. Unfortunately, in an interrupt driven system, that will not always work. The example below shows when it can fail.
Process A: |
Process B: |
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1 |
ACC := Flag |
ACC := Flag |
2 |
Test ACC=0? if not, |
Test ACC=0? if not, |
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go to start ^ |
go to start ^ |
3 |
if ACC=0: |
if ACC=0: |
4 |
Flag := 1 “printer in use” |
Flag := 1 “printer in use” |
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Access printer |
Access printer |
Flag := 0 “printer |
Flag := 0 “printer |
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not in use” |
not in use” |
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Printer Flag = 0 not in use |
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= 1 in use |
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Notice that if process A is executing instructions 1 to 4 and is interrupted by process B, then there will be two copies of the flag, one in process A’s accumulator and another in process B’s accumulator. As a result, both processes will test the flag in their local accumulator, set the flag, and proceed to use the printer.