
- •Table of Contents
- •Objectives
- •Embedded Microcomputer Applications
- •Microcomputer and Microcontroller Architectures
- •Digital Hardware Concepts
- •Voltage, Current, and Resistance
- •Diodes
- •Transistors
- •Mechanical Switches
- •Transistor Switch ON
- •Transistor Switch OFF
- •The FET as a Logic Switch
- •NMOS Logic
- •CMOS Logic
- •Mixed MOS
- •Real Transistors Don’t Eat Q!
- •Logic Symbols
- •Tri-State Logic
- •Timing Diagrams
- •Multiplexed Bus
- •Loading and Noise Margin Analysis
- •The Design and Development Process
- •Chapter One Problems
- •Organization: von Neumann vs. Harvard
- •Microprocessor/Microcontroller Basics
- •Microcontroller CPU, Memory, and I/O
- •Design Methodology
- •The 8051 Family Microcontroller
- •Processor Architecture
- •Introduction to the 8051 Architecture
- •8051 Memory Organization
- •8051 CPU Hardware
- •Oscillator and Timing Circuitry
- •The 8051 Microcontroller Instruction Set Summary
- •Direct and Register Addressing
- •Indirect Addressing
- •Immediate Addressing
- •Generic Address Modes and Instruction Formats
- •8051 Address Modes
- •The Software Development Cycle
- •Software Development Tools
- •Hardware Development Tools
- •Chapter Two Problems
- •Timing Diagram Notation Conventions
- •Rise and Fall Times
- •Propagation Delays
- •Setup and Hold Time
- •Tri-State Bus Interfacing
- •Pulse Width and Clock Frequency
- •Fan-Out and Loading Analysis—DC and AC
- •Calculating Wiring Capacitance
- •Fan-Out When CMOS Drives LSTTL
- •Transmission Line Effects
- •Ground Bounce
- •Logic Family IC Characteristics and Interfacing
- •Interfacing TTL Compatible Signals to 5 Volt CMOS
- •Design Example: Noise Margin Analysis Spreadsheet
- •Worst-Case Timing Analysis Example
- •Chapter Three Review Problems
- •Memory Taxonomy
- •Secondary Memory
- •Sequential Access Memory
- •Direct Access Memory
- •Read/Write Memories
- •Read-Only Memory
- •Other Memory Types
- •JEDEC Memory Pin-Outs
- •Device Programmers
- •Memory Organization Considerations
- •Parametric Considerations
- •Asynchronous vs. Synchronous Memory
- •Error Detection and Correction
- •Error Sources
- •Confidence Checks
- •Memory Management
- •Cache Memory
- •Virtual Memory
- •CPU Control Lines for Memory Interfacing
- •Chapter Four Problems
- •Read and Write Operations
- •Address, Data, and Control Buses
- •Address Spaces and Decoding
- •Address Map
- •Chapter Five Problems
- •The Central Processing Unit (CPU)
- •Memory Selection and Interfacing
- •Preliminary Timing Analysis
- •External Data Memory Cycles
- •External Memory Data Memory Read
- •External Data Memory Write
- •Design Problem 1
- •Design Problem 2
- •Design Problem 3
- •Completing the Analysis
- •Chapter Six Problems
- •Introduction to Programmable Logic
- •Technologies: Fuse-Link, EPROM, EEPROM, and RAM Storage
- •PROM as PLD
- •Programmable Logic Arrays
- •PAL-Style PLDs
- •Design Examples
- •PLD Development Tools
- •Simple I/O Decoding and Interfacing Using PLDs
- •IC Design Using PCs
- •Chapter Seven Problems
- •Direct CPU I/O Interfacing
- •Port I/O for the 8051 Family
- •Output Current Limitations
- •Simple Input/Output Devices
- •Matrix Keyboard Input
- •Program-Controlled I/O Bus Interfacing
- •Real-Time Processing
- •Direct Memory Access (DMA)
- •Burst vs. Single Cycle DMA
- •Cycle Stealing
- •Elementary I/O Devices and Applications
- •Timing and Level Conversion Considerations
- •Level Conversion
- •Power Relays
- •Chapter Eight Problems
- •Interrupt Cycles
- •Software Interrupts
- •Hardware Interrupts
- •Interrupt Driven Program Elements
- •Critical Code Segments
- •Semaphores
- •Interrupt Processing Options
- •Level and Edge Triggered Interrupts
- •Vectored Interrupts
- •Non-Vectored Interrupts
- •Serial Interrupt Prioritization
- •Parallel Interrupt Prioritization
- •Construction Methods
- •Power and Ground Planes
- •Ground Problems
- •Electromagnetic Compatibility
- •Electrostatic Discharge Effects
- •Fault Tolerance
- •Hardware Development Tools
- •Instrumentation Issues
- •Software Development Tools
- •Other Specialized Design Considerations
- •Thermal Analysis and Design
- •Battery Powered System Design Considerations
- •Processor Performance Metrics
- •Benchmarks
- •Device Selection Process
- •Analog Signal Conversion
- •Special Proprietary Synchronous Serial Interfaces
- •Unconventional Use of DRAM for Low Cost Data Storage
- •Digital Signal Processing / Digital Audio Recording
- •Detailed Checklist
- •1. Define Power Supply Requirements
- •2. Verify Voltage Level Compatibility
- •3. Check DC Fan-Out: Output Current Drive vs. Loading
- •4. AC (Capacitive) Output Drive vs. Capacitive Load and De-rating
- •5. Verify Worst Case Timing Conditions
- •6. Determine if Transmission Line Termination is Required
- •7. Clock Distribution
- •8. Power and Ground Distribution
- •9. Asynchronous Inputs
- •10. Guarantee Power-On Reset State
- •11. Programmable Logic Devices
- •12. Deactivate Interrupt and Other Requests on Power-Up
- •13. Electromagnetic Compatibility Issues
- •14. Manufacturing and Test Issues
- •Books
- •Web and FTP Sites
- •Periodicals: Subscription
- •Periodicals: Advertiser Supported Trade Magazines
- •Index
181CHAPTER EIGHT
Basic I/O Interfaces
damaging the relay driver circuits. Solenoid valves and other devices are used to control external flow and have similar inductive characteristics. Solid-state relays are much easier to use, as they are isolated from the high voltage and provide a simple logic level interface. Optical isolation is also used to sense high voltage inputs and convert them to logic levels. There are even standardized modules (OPTO-22 and equivalents) available that can be interchanged with each other, resulting in very flexible configuration options.
Chapter Eight Problems
1.Using an 8031 Port 1 I/O bit, design an interface to an LED that requires 20 milliamperes of output current for full brightness.
2.A DMA device transfers blocks of data consisting of 256 bytes, and the bytes in the burst are spaced 10 microseconds apart. The real time clock tick interval is 1 millisecond. What kind of DMA should be used, burst mode or single cycle?
3.If an 8031 CPU executes one instruction per microsecond, estimate the maximum rate that data can be transferred to or from an I/O port, assuming that a status bit must be polled before transferring data.
4.Design a 4-row by 3-column telephone keypad matrix for connection to the 8051 Port 1 pins, to be polled using software scanning.
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CHAPTER NINE |
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Other Interfaces
and Bus Cycles
There are two kinds of interrupts software and hardware. Software interrupts are just another kind of subroutine call that can be used to access subroutines with entry points at fixed memory locations. Operating system services are often accessed using software interrupts, which are simply instructions that cause an interrupt subroutine to be called at whatever point in the program they are placed. These interrupts are synchronized with the program in that they always occur at the same place in the program. They are referred to as “synchronous events because their execution is solely dependent upon the sequence of execution of the program instructions.
Some processor manufacturers refer to “traps” or “exceptions,” but these are synonymous with the term “interrupt” as used here, which may be either a hardware or software interrupt. Unless otherwise specified, however, the word “interrupt” is generally used to imply a hardware interrupt. Hardware interrupts are triggered by a physical event, such as the closure of a switch, that causes a specific subroutine to be called. They can be thought of as a sort of hardware initiated subroutine call. They can and do occur at any time in the program, depending on when the event occurs. These are referred to as “asynchronous events because they may occur during the execution of any part of the program. Interrupts allow the programs to respond to an event when it occurs. In a printing application, the printer may interrupt the processor to inform the program that it has printed all the data in its buffer and is ready for more. A serial interface might activate an interrupt to indicate that a character has been received and it is available to be processed. These kinds of applications are “event driven” because no action will take place until an event occurs. In the case of a typical embedded application, event driven programs are used when it is necessary to respond to an external event within a fixed time period. A system