157CHAPTER SEVEN

Programmable Logic Devices

special test pins (JTAG, boundary scan) that improve the ability of a test system to modify and observe the state of the internal logic, which makes the tests easier and faster.

Simple I/O Decoding and Interfacing Using PLDs

Programmable logic is particularly useful for decoding the addresses and control lines from a processor, because it can be used to activate the chip enable signals for the various memories and I/O chips in a system. PLDs are more flexible than standard logic for several reasons. Each of the PLD outputs can be programmed to go active when the inputs are in a particular state, such as a particular address or range of addresses. The same functions that can be decoded in a PLD would generally take several standard logic chips. This is because many of the inputs, such as address lines, are common to several of the output logic functions. Also, because the devices are programmable, the decoding logic can be changed without changing the wiring on the printed circuit board. These characteristics have made PLDs very popular, which has in turn brought their prices down to levels that are comparable to standard logic solutions. The only disadvantage to using PLDs is that they require software to “compile” the logic into binary patterns and an instrument, equivalent to a PROM programmer, which can program the device with those patterns. Each type of device requires a special programming procedure, which may be unique to the manufacturer of the PLD. Generic compilers and programmers are available, but there are devices that can only be programmed using the manufacturers proprietary software or programmer.

IC Design Using PCs

For designs that must be very inexpensive in high volume, and for designs that must fit in a tight space, a custom logic IC may be the best solution. Custom ICs (ASICs) are also becoming easier to develop with the availability of PC-based IC design tools. Because PCs have become available to almost all design engineers, computer-aided design (CAD) software has been written to run on the PC for custom and standard cell IC design as well as PLD design. Some versions of this IC CAD software can be obtained for a few thousand dollars, making it practical even for smaller firms. Some versions of this low cost software will even convert from a schematic level circuit description to a

158EMBEDDED CONTROLLER

Hardware Design

detailed IC layout that can be transmitted via modem to an IC fabrication facility. In addition, MOSIS, a joint project of government and university organizations, has been operating for many years to provide low cost IC prototypes for the government, universities, and small companies who could not afford the high costs (many thousands of dollars) for a dedicated IC prototype run. By combining multiple designs on each silicon wafer, the minimum fabrication costs are reduced to as low as approximately $500 for a design with less than 1,000 gates, with delivery of six to eight weeks. This makes it practical for every engineer to design custom and standard cell ICs. Design oriented software is also available for simulation of the chip before prototyping begins. The logic functionality can be verified by implementing early prototype chips using PLDs. Production parts can then be made in low volume using MOSIS or by other vendors in high volume at lower cost. Advantages of this approach include fewer ICs, smaller size, lower power, control of proprietary designs, and lower cost in volume. An application requiring high levels of integration, low cost in high volume, or very small size would be most appropriate for this design approach.

FPGA devices allow the designer to prototype and change custom designs and test them quickly. Some of these devices store their logic configuration in SRAM memory, allowing the hardware to be re-programmed quickly, even in the final application. The largest devices contain the equivalent of about one million gates, and processors can easily fit on these larger chips along with a great deal of other circuitry. The 8051 CPU, can fit easily into one of the moderate size devices. Large building blocks or IP cores (IP = intellectual property) can be purchased from companies that specialize in their design. The core chip building blocks include CPUs, memories, I/O devices, data converters, and so on. These complex core building blocks can be combined on a single chip to achieve “systems-on-a-chip” (SOC). This is made possible because custom ASIC, and even FPGA devices, can accommodate a number of fairly complex core blocks on a single chip. Custom ASICs have large non-recurring expenses, but have the lowest cost in moderate to high volume. Large FPGAs are very expensive (often hundreds of dollars each) so the large devices may not be suitable for high volume applications unless they must be reprogrammable in the field. Some FPGA vendors are even promoting the idea that large SRAM based FPGAs could be updated through the Internet. This would allow the ultimate consumer to upgrade their hardware as easily as upgrading the software.

159CHAPTER SEVEN

Programmable Logic Devices

Chapter Seven Problems

1.How many pins would be required on a PLD in order to implement a completely decoded memory and I/O address decoder for the design shown in Figure 7-7?

2.For the problem above, make a revised version of Table 7-1, with the input and output ports mapped to address FFFF hex.

3.Write the two equations necessary to map the I/O port select signals, / IN_EN and /OUT_CK, of Figure 7-7 to respond only to address FFFF hex.

4.If a PROM is used to implement the PLD function above, how many memory bits would be required? How many fuses would be required of a PAL style version, using the PAL shown in Figure 7-6?

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