Programmable Logic Arrays

The PLA allows the implementation of almost any sum-of-products logic function to be implemented, within the constraints of the available number of input pins, AND gates, OR gates, and output pins. While the PLA architecture allows more efficient utilization of the resources on the chip, it is also more difficult to program, as fuses must be programmed in two separate arrays. Standard memory programming devices cannot be easily modified to program a PLA with two arrays.

PLA — 4 IN - 4 OUT - 16 Products

Figure 7-6 shows a simplified example of the logic and fuse configuration used in most PAL devices. It has four inputs and four outputs which are non-inverting sums of four products.

Figure 7-5: Example of PAL fuse programming.

Figure 7-6: Typical PAL organization.

Most small PLD parts use a numbering convention that makes it easier to determine the configuration of the logic. The number is usually composed of three parts: the number of inputs to the array, output circuit type, and number of outputs. Thus a PAL with the part number 16L8 has 16 inputs to the AND array (not necessarily that many input pins), and eight active low outputs (L), while a 12H6 has 12 inputs, and six active high

(H) outputs. A device number with an “R” in it has an output register, and a “V” indicates variable or user programmable outputs. Some of the pins may