143CHAPTER SIX

A Detailed Design Example

With experience, this iterative design and analysis process becomes much easier, and potential problems are easier to anticipate. However, even with experience it is easy to become lax and leave out the review of the seemingly less important specs. This will often result in a direct application of Ken’s first law of worst-case analysis: “Any specification which is not considered will certainly be violated, causing catastrophic failure at the worst possible time.” That’s usually right before a salary review or in front of an important customer! It is important to review all the specs for the parts to be used in a design. When alternate sources for the devices are to be used, the specifications of these alternates should also be reviewed. Parts from two vendors with the exact same part number may have subtly different specs.

Chapter Six Problems

1)For this problem, use the fastest EPROM program memory from Table 6-2 (the –15 version), the 8031 CPU specs in Table 6-1, and the latch specs from Table 6-3. Ignoring the TCLCL limit on clock speed, how fast can the processor be clocked? Use the connections shown in Figure 6-3, with /PSEN connected to the EPROM /CE pin.

2)Use the same conditions as the problem above, except connect /PSEN to the EPROM /OE control.

3)For a system that has multiple program memories, an address decoder is required in order to generate separate select signals to enable the program memories. What paths and specs will be affected and how will the timing change?

4)For each of the CPU data memory write timing parameters listed in

Table 6-5, list the corresponding SRAM timing parameters from Table 6-6.

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Programmable

Logic Devices

Application specific integrated circuits (ASIC are ICs that have been designed or programmed to meet the needs of a specific design in which the chips will be used. These are differentiated from standard, or general purpose ICs that may be used in many different applications. General-purpose logic ICs are usually designed “from scratch” using only the most basic circuit elements such as transistors and gates. The cost of building a chip this way can be amortized over a large number of devices if it is used in many different applications.

When an application specific chip is designed from scratch, it is referred to as a full custom logic design. It is the lowest cost to manufacture because it takes the least amount of silicon to implement a given function. Unfortunately the design of a large full custom chip is very expensive (hundreds of thousands to millions of dollars) due to the labor-intensive design and prototyping process, and cannot be justified unless a very large quantity will be manufactured. Originally this was the only way to design chips, but now there are several alternatives for designing ASICs.

Standard cell IC design uses a library of common logic functions that have already been designed and tested. This reduces the amount of design effort in that logic IC blocks such as multiplexers are used in place of the equivalent random logic design implemented with gates. The cells can range in complexity from simple gates to complete CPUs. Standard cell based IC design has become the standard and can now be done even on a PC at a much lower cost than other methods. The cost of manufacturing a minimum production quantity of parts is less (thousands of dollars) than it would be for a full custom design process, but still high enough to be inappropriate for prototyping and low volume production (e.g., less than 5000 units).

146EMBEDDED CONTROLLER

Hardware Design

Gate arrays are fabricated with a fixed array of gates and the wiring is defined by the user when the chip is manufactured. The advantage of this approach is that the chips can be fabricated up to the point where the interconnecting wires are placed on the chip, ready for a custom interconnect. Since most of the processing is completed before the connections for any particular design are placed on the chip, these “almost finished” devices can be produced and stockpiled without any interconnects. The final interconnect can be added to define a given design, resulting in a customized version of a nearly standard part. Gate arrays are often used when the production volume is too low to justify a full custom design, but high enough so that a user programmable device is not cost effective.

User programmable logic devices (PLDs) are a family of devices that are all manufactured in the same way, and can be customized using a special programming process much like an EPROM. An EPROM can be used to implement arbitrary logic functions by using the address lines as inputs and data lines as outputs. Thus, a 1Mx8 EPROM could have eight independent logic outputs that can be any boolean function of any of the 20 input address bits. The fully completed truth table is programmed into the EPROM so that each unique input pattern will result in the appropriate data at the outputs. EPROMs are not often the best choice for the kind of logic required in most designs because of their speed and relative complexity, which translates to performance and price. Other types of devices have been designed specifically for use in those applications. There is a wide range of devices available, from fuse-linked two-level combinatorial logic and EPROM registered logic arrays, to arrays of logic blocks programmed with SRAM memory in each block. These devices span a range of complexity from one hundred to more than ten thousand usable gates. These families of devices are referred to as programmable logic arrays (PLA), programmable array logic (PAL, a registered trademark of AMD Inc.), and other trademarked names.

Field programmable gate arrays (FPGAs) are a cross between gate arrays and PLDs. They have an array of logic with user programmable interconnections. FPGAs are generally used where the desired logic function is too large to fit in a sum-of-products device, and the volume is too low to justify the use of a gate array or custom logic. FPGAs are available in sizes large enough to implement an entire CPU.