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Hardware Design

External Data Memory Cycles

Data memory read and write cycles are also examined in basically the same way, using the CPU data read cycle data and the SRAM performance specifications. The data read cycle has essentially the same three possible paths as the program read cycle, except that the CPU /RD signal is connected to the SRAM /OE input, and the SRAM chip enable is grounded.

External Memory Data Memory Read

The data memory cycle corresponds closely to the program memory cycle, as shown in the accompanying figures and tables. Figure 6-6 illustrates the timing relationship between the CPU and external SRAM data memory when the CPU

NOTE: There are 2 to 8 ALE cycles per instruction. Clocks and state timing are shown on the timing diagram for reference purposes only. They are not accessible outside the package. TCY is the minimum instruction cycle time that consists of 12 oscillator clocks or two ALE cycles. Address setup and hold times are the same for data and program memory.

Table 6-4: 8031 data memory timing parameters.

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Hardware Design

address. The -15 version of the SRAM has an address access time of 150 nS max. (SRAM tAA), so there is 450 nS of margin for this memory at this clock speed!

TAVDV - SRAM tAA = 600 - 150 = 450 nS margin

B)Even allowing for an additional 16 nS through the address latch for address bits 0..7, there is still a margin of 434 nS, so there is no problem with address access time.

TAVDV - SRAM tAA - Latch tPmax = 600 - 150 -16 = 434 nS margin

C)This is the time available to the memory after /RD goes low and when valid data is on the bus. The enable access time provided by the CPU is 250 nS (TRLDV). Since the slowest RAM, the -15 version, has an OE access time of 70 nS (tOE), there is 180 nS of design margin.

External Data Memory Write

Figure 6-8 and Table 6-6 show the SRAM write cycle diagram and timing parameters. Figure 6-9 shows a data memory write timing diagram for the 8031.

Figure 6-8: SRAM write cycle timing diagram.

137CHAPTER SIX

A Detailed Design Example

Figure 6-9: 8031 data memory write timing.

From the CPU specifications, the address is valid 200 nS (TAVWL) before the /WR line goes low, and the data is valid 400 nS (TQVWH) before the /WR line goes high. The RAM requires an address setup before write time of 0 nS, which is compatible with the 200 nS provided by the CPU. The RAM data setup time before the end of the /WE pulse (SRAM spec tDW) is 60 nS, which is well within the 400 nS available. The latch delay has been ignored here because it is 16 nS, which is insignificant compared to the design margin available. Also, the chip select input of the RAM is grounded, so the chip select access time does not need to be considered. The minimum write pulse width from the CPU is 400 nS (TWLWH), and the RAM requires only a minimum of 90 nS (tWP), so the pulse width is well within the spec. The RAM has a 0 nS hold time requirement (tDH), and the processor provides 80 nS (TWHQX), so the RAM hold time requirement is also met with margin.