115CHAPTER FOUR
Memory Technologies and Interfacing
special system software, it is possible to make the main memory appear much larger than it actually is to a program running on this type of machine. When the program attempts to access a location that is not present in the main memory, the hardware and software redirect the memory reference to a real block of memory, after the required data is loaded from disk. Thus the application program is presented with a virtual memory that is significantly larger than the actual physical main memory. This has the effect of simplifying the code, since all data can be referenced by a single address, rather than selecting a file, track, or sector on a disk.
CPU Control Lines for Memory Interfacing
Some CPUs generate signals for memory timing and synchronization with devices having various access times using a technique that generates delay cycles for slow memories, referred to as wait states. The 8051 processor used in this text does not use or generate wait states for simplicity. The Dallas 80C320 series of high speed microcontrollers incorporate a software-controlled mechanism for generating wait states. These extended memory cycles allow the processor to work with slower memory and peripheral chips.
Chapter Four Problems
1.What is the largest capacity SRAM that will fit in a 32-pin package?
2.What is the largest ROM that will fit in a 32-pin package?
3.Using 4M x 4 DRAMs, how many chips will be required to implement a 16 megabyte memory organized in 32-bit words?
4.What restrictions must be considered, when writing software to program an EEPROM device?
5.What restrictions are imposed when writing to flash EPROM?
6.What would you expect to read from a blank EPROM, if its data storage element is an N-channel FET that is connected with its source grounded and the drain connected to an output pin and a pull-up resistor?
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CHAPTER FIVE |
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CPU Bus Interface
and Timing
The central processing unit (CPU) is the key part of a microcomputer, both from the functional aspect and from the design procedure facet. This is because the key control signals originate from the CPU, driving most of the timing, load, and functional characteristics of the bus interface that all other devices must be compatible with. The processor controls the data transfers on the bus on a cycle- by-cycle basis, fetching instructions, reading and writing operand data. Let’s begin by examining how the CPU reads data from and writes data to memory.
Read and Write Operations
Refer to Figure 5-1 as you read through the following steps in a memory read operation:
1)The CPU selects the memory location by driving the address on the address bus.
2)Control lines are driven by the CPU to indicate the address space to use, such as program memory, data memory, I/O, or special cycles such as interrupts.
3)Read is activated on the control bus by the CPU to indicate that the memory can drive the data bus with the contents of the selected location.
4)The memory drives the contents of the selected location on the data bus.
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118EMBEDDED CONTROLLER
Hardware Design
Refer to Figure 5-2 as you read through the following steps in a memory write operation:
1)The CPU selects the memory location by driving the address on the address bus.
2)Control lines are driven by the CPU to indicate the address space to use.
3)The CPU drives the data to be written on the data bus.
4)Write is activated on the control bus by the CPU to indicate that the data on the data bus should be written into the selected location.
5)The CPU deactivates the address, data, and control lines.
Memory Write Cycles
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Figure 5-2: Generic CPU writing data to memory.
Address, Data, and Control Buses
During normal operation, the CPU drives the address bus with the location to be transferred to or from the CPU. Addresses generally refer to memory locations or I/O locations. The data stored in those locations is usually eight bits (a byte), 16 bits, or 32 bits depending on the processor. Most microcontrollers use byte addressing, meaning that each address is a pointer to an 8-bit piece of data. Most 8-bit and virtually all 16and 32-bit processors can also address and manipulate data in 16and 32-bit pieces. Directly accessible addresses are those that the CPU can access in a single cycle using the address bus. If a processor has N address bits, then it can directly address 2N locations, starting at location 0 and increasing to location 2N-1. Typical processors may have 16-, 20-, 24-, or 32-bit address buses. A byte addressing, 16-bit processor can address 216 locations, or 65,536 = 64 kilobytes. Likewise, a processor with a 20-bit address bus can directly access 220 locations, or one megabyte. Some locations of memory may not be directly accessible by the CPU, meaning that the CPU must use multiple cycles to access one memory location, usually under software control. This technique, sometimes referred to as bank switching, is the so-called “expanded memory above one megabyte in the PC, which uses an 8088 CPU with 20 address bits.
119CHAPTER FIVE
CPU Bus Interface and Timing
The 80286 CPU has 24 address bits allowing direct addressing of 224 or 16 megabytes. The 80386 and higher processors have a 32-bit address space, addressing up to 232 or 4 gigabytes. Some processors use a subset of the address lines for I/O. If the processor instructions use a 16-bit address field in the I/O instructions for example, then only 216 I/O locations are accessible.
The data bus, driven by the CPU during write cycles and by other devices during read cycles, transfers instructions and data in and out of the CPU. The width of the data bus, among other things, determines the amount of data that can be transferred on the bus. This data throughput is referred to as the bus bandwidth and is usually expressed in bytes per second. If a bus supports one transfer per microsecond, an 8-bit bus has a one megabyte per second bandwidth, a 16-bit bus has a two megabytes per second bandwidth, and a 32-bit bus has four megabytes per second bandwidth. In the case of an 8-bit bus and a period T =1 microsecond ( S), then f = 1/T = 1 MHz and, for one byte per cycle, the result is one megabyte per second or eight megabits per second.
The control bus, normally driven by the CPU, determines what type of cycle is to take place and when the data will be present on the bus. In the case of a processor with a multiplexed address and data bus, some or all of the data bus is multiplexed or shared with the address bus. An additional signal is provided on the control bus to enable an address storage latch to hold the address information at the beginning of a transfer cycle. Bus cycles on a multiplexed address/data bus system, as shown in Figure 5-3, are identical to those illustrated previously except for the addition of address information on the data bus at the beginning of a cycle, and an address latch control signal as shown in Figure 5-3. The 8051 has a multiplexed bus cycle.
Multiplexed Bus Cycles
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Figure 5-3: Multiplexed address/data bus cycles.