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each instruction cycle requires a multiple of 12 clock cycles. For the Dallas high-speed CPU versions, four clock cycles are used for most instruction cycles.

In most 8051 designs, the capacitors connected to the crystal should be in the 10 to 50 picofarads range, with 30 picofarads being a typical value. The crystal should be an “AT cut” series resonant device. The “AT” designation refers to the way the quartz crystal is cut from the blank with an orientation relative to the crystal lattice that reduces the crystal’s frequency dependence on temperature changes. The crystal is manufactured so that it is series resonant at the specified frequency. A given crystal will resonate in a series or parallel mode. A parallel resonant crystal will still operate in the circuit, but it will operate at a slightly different frequency. Actual operating frequency depends on the load capacitance, and is subject to temperature, and will drift over time.

Selection of the capacitors is a trade-off between oscillator start-up time and stability. Specification of a crystal depends upon the specific design requirements and the processor being used. Even parts with the same number may have different requirements, especially for parts from different manufacturers.

There’s much more information available from the crystal and processor manufacturers on the proper design and operation of crystal oscillators. Other frequency references, such as ceramic resonators and even simple R-C circuits can be used for many processors. Some microcontrollers even include on-chip oscillators that can be calibrated to operate at a specific frequency, albeit with less accuracy and greater drift. Application note AP-155, “Oscillators for Microcontrollers” from Intel Corporation, is a very useful reference and describes the characteristics of both the crystal and ceramic resonator’s operation as well as the processor’s oscillator amplifier.

The 8051 Microcontroller Instruction Set Summary

The following description of the instruction set is not a complete list, but serves to introduce the general character of the standard 8051 instructions. The instruction set utilized by the 8051 microcontroller consists of a total of 111 instructions, which may be divided up into several different categories. These are:

1.Arithmetic (24)

2.Logical (25)

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3.Data transfer (28)

4.Bit (Boolean) variable manipulation (17)

5.Program branching and control (17)

Each of these categories is comprised of instructions that utilize mnemonics as shown below:

Arithmetic

ADD, ADDC, SUBB, INC, DEC, MUL, DIV, DA

Logical

ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP

Data Transfer

MOV, MOVX, MOVC, PUSH, POP, XCH, XCHD

Bit (Boolean) Variable Manipulation

CLR, SETB, CPL, ANL, ORL, MOV, JC, JNC, JB, JNB, JBC

Program Branching and Control

ACALL, LCALL, RET, RETI, AJMP, LJMP, SJMP, JMP, JZ, JNZ, CJNE, DJNZ, NOP

Direct and Register Addressing

While the number of mnemonics is clearly smaller in number than the total of 111 instructions, a given mnemonic may be used in several different ways to make up a valid 8051 instruction. These different ways of forming instructions are classified by the types of arguments that a given mnemonic takes. A mnemonic can refer to data in a number of ways. One can refer to data located in particular address in the data memory space either by specifying its address directly, or indirectly by using a data pointer register. In this case, the data pointer register contains the address of the memory location we seek. The 8051 looks in the data pointer register, and then retrieves the information located in the location referred to (or pointed to) by the data pointer. Additionally, the 8051 has 32 bytes of internal memory divided up into four register banks of eight bytes each. These register banks may be referred to in an 8051 instruction by either their direct address (which ranges between 00h and 1Fh), or by their register

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name, which is denoted by R0 through R7. When these memory locations are addressed by their register name, it is important to remember which register bank is currently in use. These register banks, numbered 0 through 3, are selected through two bits located in a special register called the program status word (PSW). The PSW contains a number of very important bits, which are used to indicate the current status of the processor. Note that because the registers R0 through R7 are located in the data memory space, they may be addressed either by the register name or by their direct address location. Consider the instruction:

MOV A,R3

This instruction takes the contents of register R3 and moves it (actually, the data is copied) to a register denoted by the letter “A”, called the accumulator. The accumulator is the “working” register of the 8051, and is the register that is used in most all arithmetic and logical operations performed by the processor.

Assuming we are using register bank 0, the following instruction is identical to the instruction just shown:

MOV A,03h

Since register R3 is at internal RAM location 03h, the above instruction takes the data stored in RAM location 03h and moves it to the accumulator.

What is the difference between these two forms of saying the same thing? The first instruction is called register addressing, while the second instruction is called direct addressing. The reason for the difference in nomenclature is obvious, and while it may seem a bit pointless to dwell on the difference between these two modes, there is a significant difference in the way the 8051 deals with each type of addressing.

Looking in the 80C51-Based 8-Bit Microcontrollers Data Book (publication number IC-20) published by Philips, the instruction MOV A,R3 takes up only one byte of program memory space, while the instruction MOV A,03h requires two bytes of program memory space. The reason the register mode instruction requires less program memory to store is that a reference to a register requires three bits to represent its address, and a reference to an arbitrary location in internal data memory requires 8 bits. Once a particular register bank is selected by setting the proper bits in the PSW, any register in that bank may be completely determined by only 3 bits (3 bits are required to distinguish eight

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possible locations). If we use direct mode to perform the very same operation, we now require 7 bits to completely determine the exact location out of 128 possible locations—thus, direct addressing instructions generally occupy more program memory space than register addressing instructions.

There are two other memory locations in the 8051 that may be addressed through register mode. These are the accumulator, which we have already seen is denoted by the letter “A,” and the data pointer, which is actually two registers. The letters DPTR denotes the data pointer, and is a 16-bit quantity used for addressing locations in data memory external to the microcontroller itself. Since the DPTR is a 16-bit quantity, a total of 64 kilobytes of data may be addressed. This is, of course, the maximum data that may be accessed at any one time by the 8051.

The following instructions are examples of data movement instructions that utilize direct addressing:

The following instructions are examples of data movement instructions, which utilize register addressing:

Note that in all instructions, the order of the memory locations in the instruction is always destination, source. The destination address appears first, followed by the source address.

The instructions PUSH and POP perform operations on a portion of memory called the stack. While not a separate memory space, the stack is located in the internal data memory portion of the 8051/52, and is structured as a LIFO (last in, first out) data structure.