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Моделирование плм в программе схемотехнического моделирования Tanner t-Spise Pro

Изображение схемы в модуле S-Edit

Текст программы полученный в модуле T-Spise:

* SPICE netlist written by S-Edit Win32 6.02

* Written on May 20, 2004 at 09:32:07

* Waveform probing commands

.probe

.options probefilename="PLM.dat"

+ probesdbfile="C:\Documents and Settings\eugene\Рабочий стол\МИЭМ\Схемотехника ЭВМ\Tanner\PLM.sdb"

+ probetopmodule="Module0"

* No Ports in cell: PageID_Tanner

* End of module with no ports: PageID_Tanner

.SUBCKT Inv A Out Gnd Vdd

M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1

* Page Size: 5x7

* S-Edit Inverter (TIB)

* Designed by: J. Luo Apr 28, 2004 12:01:17

* Schematic generated by S-Edit

* from file C:\Documents and Settings\eugene\Рабочий стол\МИЭМ\Схемотехника ЭВМ\Tanner\PLM / module Inv / page Page0

M1 Out A Vdd Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1

.ENDS

* Main circuit: Module0

.param l=1u

Q1 N75 N18 y2 NPN area=1

Q2 N4 N9 y3 NPN area=1

Q3 N4 N3 y3 NPN area=1

Q4 N45 N3 y1 NPN area=1

Q5 N74 N8 y4 NPN area=1

Q6 N74 N20 y4 NPN area=1

Q7 N45 N11 y1 NPN area=1

Q8 N15 N20 y5 NPN area=1

Q9 N15 N8 y5 NPN area=1

Q10 N67 N18 y6 NPN area=1

Q11 N67 N3 y6 NPN area=1

Q12 N66 N3 y7 NPN area=1

Q13 N66 N13 y7 NPN area=1

Q14 N66 N9 y7 NPN area=1

Q15 N66 N22 y7 NPN area=1

Q16 N35 N24 y8 NPN area=1

Q17 N70 N24 y9 NPN area=1

Q18 N71 N24 y10 NPN area=1

Q19 N70 N22 y9 NPN area=1

Q20 N70 N3 y9 NPN area=1

Q21 N71 N11 y10 NPN area=1

Q22 N71 N18 y10 NPN area=1

Q23 N75 N32 y2 NPN area=1

Q24 N75 N27 y2 NPN area=1

Q25 N49 N30 y3 NPN area=1

Q26 N74 N28 y4 NPN area=1

Q27 N15 N31 y5 NPN area=1

Q28 N15 N40 y5 NPN area=1

Q29 N67 N34 y6 NPN area=1

Q30 N67 N37 y6 NPN area=1

Q31 N67 N39 y6 NPN area=1

Q32 N35 N29 y8 NPN area=1

Q33 N35 N57 y8 NPN area=1

Q34 N35 N26 y8 NPN area=1

Q35 N70 N61 y9 NPN area=1

Q36 N70 N58 y9 NPN area=1

Q37 N45 N12 y1 NPN area=1

Q38 N71 N56 y10 NPN area=1

Q39 N45 N13 y1 NPN area=1

D40 N11 N53 DIODE area=1

D41 N11 N33 DIODE area=1

D42 N11 x3 DIODE area=1

D43 N32 N54 DIODE area=1

D44 N3 N54 DIODE area=1

D45 N11 x4 DIODE area=1

D46 N3 x4 DIODE area=1

D47 N3 N53 DIODE area=1

D48 N12 x4 DIODE area=1

D49 N12 N54 DIODE area=1

D50 N12 x2 DIODE area=1

D51 N13 N55 DIODE area=1

D52 N13 x2 DIODE area=1

D53 N13 N53 DIODE area=1

D54 N18 N55 DIODE area=1

D55 N18 x3 DIODE area=1

D56 N18 x2 DIODE area=1

D57 N18 x1 DIODE area=1

D58 N9 x3 DIODE area=1

D59 N9 N53 DIODE area=1

D60 N8 x4 DIODE area=1

D61 N8 x3 DIODE area=1

D62 N8 x2 DIODE area=1

D63 N20 N55 DIODE area=1

D64 N20 x3 DIODE area=1

D65 N20 N33 DIODE area=1

D66 N20 x1 DIODE area=1

D67 N22 x4 DIODE area=1

D68 N22 x3 DIODE area=1

D69 N22 x1 DIODE area=1

D70 N22 N33 DIODE area=1

D71 N24 N55 DIODE area=1

D72 N24 x3 DIODE area=1

D73 N32 x1 DIODE area=1

D74 N24 N33 DIODE area=1

D75 N24 N53 DIODE area=1

D76 N27 N55 DIODE area=1

D77 N27 N54 DIODE area=1

D78 N27 N33 DIODE area=1

D79 N30 N55 DIODE area=1

D80 N30 N54 DIODE area=1

D81 N30 x2 DIODE area=1

D82 N30 x1 DIODE area=1

D83 N28 x4 DIODE area=1

D84 N28 N54 DIODE area=1

D85 N28 x1 DIODE area=1

D86 N31 x1 DIODE area=1

D87 N31 N54 DIODE area=1

D88 N31 N55 DIODE area=1

D89 N34 x4 DIODE area=1

D90 N37 x4 DIODE area=1

D91 N29 x4 DIODE area=1

D92 N56 x4 DIODE area=1

D93 N57 N55 DIODE area=1

D94 N58 N55 DIODE area=1

D95 N61 x3 DIODE area=1

D96 N26 x3 DIODE area=1

D97 N57 N54 DIODE area=1

D98 N29 N54 DIODE area=1

D99 N39 N54 DIODE area=1

D100 N40 N54 DIODE area=1

D101 N46 x2 DIODE area=1

D102 N44 x2 DIODE area=1

D103 N57 x2 DIODE area=1

D104 N26 x2 DIODE area=1

D105 N61 x2 DIODE area=1

D106 N58 x2 DIODE area=1

D107 N56 x1 DIODE area=1

D108 N58 x1 DIODE area=1

D109 N26 x1 DIODE area=1

D110 N40 N33 DIODE area=1

D111 N34 N33 DIODE area=1

D112 N39 N33 DIODE area=1

D113 N34 x1 DIODE area=1

D114 N61 N53 DIODE area=1

D115 N39 N53 DIODE area=1

D116 N37 N53 DIODE area=1

D117 N40 N53 DIODE area=1

XInv_1 x4 N55 Gnd Vdd Inv

XInv_2 x3 N54 Gnd Vdd Inv

XInv_3 x2 N33 Gnd Vdd Inv

XInv_4 x1 N53 Gnd Vdd Inv

R118 N1 N11 1500 TC=0.0, 0.0

R119 N1 N3 1500 TC=0.0, 0.0

R120 N1 N12 1500 TC=0.0, 0.0

R121 N1 N13 1500 TC=0.0, 0.0

R122 y1 Gnd 1500 TC=0.0, 0.0

R123 N1 N18 1500 TC=0.0, 0.0

R124 N1 N9 1500 TC=0.0, 0.0

R125 N1 N8 1500 TC=0.0, 0.0

R126 N1 N20 1500 TC=0.0, 0.0

R127 N1 N22 1500 TC=0.0, 0.0

R128 N1 N24 1500 TC=0.0, 0.0

R129 y2 Gnd 1500 TC=0.0, 0.0

R130 N1 N32 1500 TC=0.0, 0.0

R131 N1 N27 1500 TC=0.0, 0.0

R132 N1 N30 1500 TC=0.0, 0.0

R133 N1 N28 1500 TC=0.0, 0.0

R134 N1 N31 1500 TC=0.0, 0.0

R135 y3 Gnd 1500 TC=0.0, 0.0

R136 y4 Gnd 1500 TC=0.0, 0.0

R137 y5 Gnd 1500 TC=0.0, 0.0

R138 y6 Gnd 1500 TC=0.0, 0.0

R139 y7 Gnd 1500 TC=0.0, 0.0

R140 y8 Gnd 1500 TC=0.0, 0.0

R141 y9 Gnd 1500 TC=0.0, 0.0

R142 y10 Gnd 1500 TC=0.0, 0.0

R143 N1 N40 1500 TC=0.0, 0.0

R144 N1 N34 1500 TC=0.0, 0.0

R145 N1 N37 1500 TC=0.0, 0.0

R146 N1 N39 1500 TC=0.0, 0.0

R147 N1 N29 1500 TC=0.0, 0.0

R148 N1 N57 1500 TC=0.0, 0.0

R149 N1 N26 1500 TC=0.0, 0.0

R150 N1 N61 1500 TC=0.0, 0.0

R151 N1 N58 1500 TC=0.0, 0.0

R152 N1 N56 1500 TC=0.0, 0.0

v153 x3 Gnd bit({0000111100001111} pw=100n on=5.0 off=0.0 rt=3n ft=3n delay=0 lt=20n ht=20n)

v154 x4 Gnd bit({0000000011111111} pw=100n on=5.0 off=0.0 rt=3n ft=3n delay=0 lt=20n ht=20n)

v155 x2 Gnd bit({0011001100110011} pw=100n on=5.0 off=0.0 rt=3n ft=3n delay=0 lt=20n ht=20n)

v156 x1 Gnd bit({0101010101010101} pw=100n on=5.0 off=0.0 rt=3n ft=3n delay=0 lt=20n ht=20n)

v157 N1 Gnd 5.0

v158 N45 Gnd 5.0

v159 N75 Gnd 5.0

v160 N4 Gnd 5.0

v161 N74 Gnd 5.0

v162 N15 Gnd 5.0

v163 N67 Gnd 5.0

v164 N66 Gnd 5.0

v165 N35 Gnd 5.0

v166 N70 Gnd 5.0

v167 N71 Gnd 5.0

* End of main circuit: Module0

.model npn npn

.model diode d

.include "C:\Program Files\Tanner EDA\T-Spice Pro v6.02\models\ml2_20.md"

.tran/op 0.1n 320n method=bdf

.print tran v(x1) v(x2) v(x3) v(x4)

Переходная характеристика полученная в модуле W-Edit:

Входы X1, X2, X3, X4

Выходы Y1, Y2, Y3, Y4, Y5

Выходы Y6, Y7, Y8, Y9, Y10

Проектирование схемы сравнения.

Y1

Y2

S1

S2

C1

C2

0

0

0

0

0

1

0

1

0

0

0

1

0

1

2

0

0

1

0

0

1

3

0

0

1

1

0

1

4

0

1

0

0

0

1

5

0

1

0

1

1

0

6

0

1

1

0

0

1

7

0

1

1

1

0

1

8

1

0

0

0

0

1

9

1

0

0

1

0

1

10

1

0

1

0

1

0

11

1

0

1

1

0

1

12

1

1

0

0

0

1

13

1

1

0

1

0

1

14

1

1

1

0

0

1

15

1

1

1

1

1

0

Алгоритм работы схемы сравнения

Если (Y1,Y2) = (S1,S2) , то (Y3…Y10) => Рг 2,

Иначе => Рг 3

Задержка схемы сравнения - 2 τ, мощность 12 Р.

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