Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
Cadence / DSD 4 / Топология.doc
Скачиваний:
26
Добавлен:
16.04.2013
Размер:
479.23 Кб
Скачать

Фрагмент правил для разработки топологии (Physical Design Rules).

1A Minimum NWELL width 1.Oum

1B Minimum NWELL space 1.Oum

1D Minimum PWELL width 1.Oum

1E Minimum PWELL space 1.Oum

2A Minimum OXIDE width 0.4um

2B Minimum OXIDE space 0.3um

2C Minimum NWELL enclosure of OXIDE 0.5um

2D Minimum NWELL to OXIDE space 0.5um

3A Minimum NIMP width 0.4um

3B Minimum NIMP space 0.4um

3C Minimum NIMP enclosure of OXIDE 0.2um

4A Minimum PIMP width 0.4um

4B Minimum PIMP space 0.4um

4C Minimum PIMP enclosure of OXIDE 0.2um

4E PIMP and NIMP cannot overlap

5A Minimum POLY width 0.18um

5B Minimum POLY space 0.3um

5C Minimum POLY extension beyond OXIDE (poly endcap) 0.2um

5D Minimum OXIDE extension beyond gate POLY 0.4um

5E Minimum Poly to OXIDE spacing 0.2um

6A Minimum and maximum width of CONT 0.2um

6B Minimum CONT space 0.2um

6C Minimum OXIDE enclosure of CONT 0.2um

6D Minimum POLY enclosure of CONT 0.2um

6E Minimum POLY to CONT space 0.2um

6F Minimum NIMP enclosure of CONT 0.2um

6G Minimum PIMP enclosure of CONT 0.2um

7A Minimum METAL1 width 0.3um

7B Minimum METAL1 space 0.3um

7C Minimum METAL1 enclosure of CONT 0.lum

8A Minimum and maximum width of VIA1 0.2um

8B Minimum VIA1 space 0.3um

8C Minimum METAL1 enclosure of VIA1 0.lum

9A Minimum METAL2 width 0.3um

9B Minimum METAL2 space 0.3um

9C Minimum METAL2 enclosure of VIA1 0.lum

……………………………………………

13A Maximum distance from a source/drain OXIDE region to the nearest well tie lOum

Фрагмент описания элемента UNVERTOR на Verilog

`timescale 1ns/10ps

`celldefine

module INVX1 (Y, A);

output Y;

input A;

not I0(Y, A);

specify

// delay parameters

specparam

tplh$A$Y = 0.03,

tphl$A$Y = 0.02;

// path delays

(A *> Y) = (tplh$A$Y, tphl$A$Y);

endspecify

endmodule // INVX1

`endcelldefine

Фрагмент технологического LEF-файла цифровой библиотеки

VERSION 5.3 ;

NAMESCASESENSITIVE ON ;

UNITS

DATABASE MICRONS 2000 ;

END UNITS

LAYER POLY1

TYPE MASTERSLICE ;

END POLY1

LAYER METAL1

TYPE ROUTING ;

WIDTH 0.230 ;

SPACING 0.230 ;

SPACING 0.6 RANGE 10.0 100000.0 ;

PITCH 0.560 ;

DIRECTION HORIZONTAL ;

RESISTANCE RPERSQ 8.7000e-02 ;

CAPACITANCE CPERSQDIST 1.2903e-04 ;

EDGECAPACITANCE 5.7961e-05 ;

END METAL1

LAYER VIA12

TYPE CUT ;

END VIA12

LAYER METAL2

TYPE ROUTING ;

WIDTH 0.280 ;

SPACING 0.280 ;

SPACING 0.6 RANGE 10.0 100000.0 ;

PITCH 0.660 ;

DIRECTION VERTICAL ;

RESISTANCE RPERSQ 8.7000e-02 ;

CAPACITANCE CPERSQDIST 7.2791e-05 ;

EDGECAPACITANCE 4.9793e-05 ;

END METAL2

LAYER VIA23

TYPE CUT ;

END VIA23

Фрагмент lef-файла описания элемента unvertor

MACRO INVXL

CLASS CORE ;

FOREIGN INVXL 0.000 0.000 ;

ORIGIN 0.000 0.000 ;

SIZE 1.320 BY 5.040 ;

SYMMETRY x y ;

SITE slt1site ;

PIN Y

DIRECTION OUTPUT ;

PORT

LAYER METAL1 ;

RECT 1.030 2.380 1.180 3.225 ;

RECT 1.030 1.350 1.120 1.845 ;

RECT 0.800 1.350 1.030 3.225 ;

RECT 0.780 1.350 0.800 1.845 ;

END

END Y

PIN A

DIRECTION INPUT ;

PORT

LAYER METAL1 ;

RECT 0.140 1.820 0.520 2.510 ;

END

END A

PIN VSS

DIRECTION INOUT ;

USE ground ;

SHAPE ABUTMENT ;

PORT

LAYER METAL1 ;

RECT 0.990 -0.400 1.320 0.400 ;

RECT 0.180 -0.400 0.990 0.575 ;

RECT 0.000 -0.400 0.180 0.400 ;

END

END VSS

PIN VDD

DIRECTION INOUT ;

USE power ;

SHAPE ABUTMENT ;

PORT

LAYER METAL1 ;

RECT 0.850 4.640 1.320 5.440 ;

RECT 0.850 3.820 1.085 4.160 ;

RECT 0.510 3.820 0.850 5.440 ;

RECT 0.275 3.820 0.510 4.160 ;

RECT 0.000 4.640 0.510 5.440 ;

END

END VDD

END INVXL

Соседние файлы в папке DSD 4