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ivanov666
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Предмет:
Файл:Языки VHDL и VERILOG в проектировании цифровой аппаратуры
.pdf
Глава 7. Функциональная модель микросхемы двухпортовой памяти 221
ELSE
int_sdram( address_trans (ar_reg)):=STD_MEMDATA_TO_BIGINTEGER(HIX);
print_addrmsg (text =>InstancePath & partID &
"Collision when WRITE to BOUTH mem ports,'X' val was written",
addr =>al_reg);
END IF;
END IF;
END IF;
-- параллельно ЗАПИСЬ В ПРАВЫЙ –ЧТЕНИЕ ИЗ ЛЕВОГО
IF ( (now-time_r_write)<tCCS) AND (( now -time_l_read)<tCCS )
AND (addr_r_write =addr_l_read) THEN
IF XOn THEN
data_vx := HIX;
datal_reg <= data_vx;
END IF;
print_addrmsg (text =>InstancePath & partID &
"**** Collision when READ from LEFT mem port,OUT DATA =X",
addr =>al_reg);
-- одновременно запись в левый -чтение из правого
ELSIF (now-time_l_write)<tCCS AND (now -time_r_read)<tCCS
AND (addr_l_write =addr_r_read) THEN
IF XOn THEN
data_vx := HIX;
datar_reg <= data_vx;
END IF;
print_addrmsg (text =>InstancePath & partID &
"**** Collision when READ from RIGHT mem port ,OUT DATA =X",
addr =>ar_reg);
END IF;
END IF;
----------------------END PROCESS;
----ВЫХОДНЫЕ ДРАЙВЕРЫ шины ПАМЯТИ
--возможны варианты с заданием X на выходе памяти
-- в переходном режиме в промежутках между
--предустановкой -hold и удержанием setup
process(datar_reg)
begin
if(( datar_reg /= ior_int) AND outXon) then
ior_int<=(others=>'X')after tDC, datar_reg after tCD2;
else
ior_int<=datar_reg after tCD2;
end if;
end process;
process(datal_reg)
begin
if( (datal_reg /=iol_int)AND outXon ) then
iol_int<=(others=>'X')after tDC, datal_reg after tCD2;
else
iol_int<= datal_reg after tCD2;
end if;
end process;
222 Глава 7. Функциональная модель микросхемы двухпортовой памяти
--ЗАДЕРЖКА OE -----------------------oeld_n <= '1' after tOHZ when OEL_n ='1' ELSE '0' after tOLZ,'0' after tOE;
oerd_n <= '1' after tOHZ when OER_n ='1' ELSE '0' after tOLZ,'0' after tOE;
-----ВЫХОДНЫЕ ТРЕХСТАБИЛЬНЫЕ БУФЕРА---------------------------------
--ЛЕВЫЙ ПОРТ -------------------process(oeld_n,cs2l_reg,rwl_reg,iol_int, tx_viol_reg)
begin
if (cs2l_reg='1') and( oeld_n='0')and( rwl_reg='0') then--read
iol<=iol_int;
elsif(( cs2l_reg='0') OR ( oeld_n='1')OR ( rwl_reg='1') ) then
iol<=(others=>'Z') ;
else
iol<= (others=>'X');
end if;
-- if(tx_viol_reg /='0') then
-- iol<=(others=>'X') ;--change dout when timing viol
-- end if;
end process;
PROCESS (tx_viol,CLKL)
BEGIN
IF (tx_viol'EVENT AND tx_viol ='X') AND XOn THEN
tx_viol_reg<='1' ;
ELSIF CLKL'EVENT AND CLKL='1' THEN
tx_viol_reg<='0' ;
END IF;
END PROCESS;
--ПРАВЫЙ ПОРТ – описание опущено-оно подобно левому порту
-- но в именах сигналов буква r вместо l
---- ВЫЗОВ( КОНКРЕТИЗАЦИЯ) МОДУЛЯ ВРЕМЕННЫХ ПРОВЕРОК--TIME_VIOL_CHECK: entity dual_port_ramv_timing_check
GENERIC MAP (
Device_Type=> Device_Type,
data_length => data_length,
addr_length=>addr_length,
-- timing check control parameters
InstancePath => InstancePath,
partID => partID,
TimingChecksOn =>TimingChecksOn,
MsgOn => MsgOn,
XOn => XOn
)
PORT MAP(
AL =>AL, AR=> AR, RWL=>RWL,
RWR=> RWR, OEL_n=> OEL_n,
OER_n=>OER_n, IOL =>IOL,
IOR =>IOR, CLKL=>CLKL,
CLKR=>CLKR, CE0L_n=>CE0L_n,
CE1L=> CE1L, CE0R_n=>CE0R_n,
CE1R =>CE1R,
----ADDITIONAL PORTS FOR change funct when violation-----tx_viol =>tx_viol, ty_viol =>ty_viol
);
END vhdl_behavioral ; -- OF dual_port_ramv_vh
Глава 7. Функциональная модель микросхемы двухпортовой памяти 223
7.4.3. Пакет со значениями временных
параметров
-- File name : dual_port_ramv_timing_data.vhd
PACKAGE dual_port_ramv_timing_data IS
----------------------------------------------------
-- Common Types to pass timing parameters
-----------------------------------------TYPE MaxFreqVal IS (f83,f67); -- MHZ
TYPE DevTimeArr IS ARRAY (MaxFreqVal) OF TIME;
--CLOCK---CONSTANT tCYC2_arr : DevTimeArr := (12 ns, 15 ns); --min
CONSTANT tCH2_arr : DevTimeArr := ( 4 ns,6.0 ns ); -- min
CONSTANT tCL2_arr : DevTimeArr := ( 4 ns,6.0 ns ); -- min
CONSTANT tR_arr : DevTimeArr := (3 ns,3 ns); -- max
CONSTANT tF_arr : DevTimeArr := (3 ns,3 ns); -- max
--addr SETUP hold TIME--------CONSTANT tSA_arr : DevTimeArr := (2.5 ns,2.5 ns); -- min
CONSTANT tHA_arr : DevTimeArr := (0.5 ns,0.5 ns); -- min
--chip enable
CONSTANT tSC_arr : DevTimeArr := (2.5 ns,2.5 ns); -- min
CONSTANT tHC_arr : DevTimeArr := (0.5 ns,0.5 ns); -- min
--RW
CONSTANT tSW_arr : DevTimeArr := (2.5 ns,2.5 ns); -- min
CONSTANT tHW_arr : DevTimeArr := (0.5 ns,0.5 ns); -- min
-- data delay
CONSTANT tSD_arr : DevTimeArr := (2.5 ns,2.5 ns); -- min
CONSTANT tHD_arr : DevTimeArr := (0.5 ns,0.5 ns); -- min
--OUTPUT DELAY TIMES----
--oe to data valid
CONSTANT tOE_arr : DevTimeArr := (6.0 ns, 6.5 ns); -- max
--oe to low z
CONSTANT tOLZ_arr : DevTimeArr := (1 ns, 1 ns); -- min
--oe to h z
CONSTANT tOHZ_arr : DevTimeArr := (3.0 ns, 3.0 ns); -- max
-- clk to data valid
CONSTANT tCD2_arr : DevTimeArr := (6.0 ns, 6.5 ns); -- max
--data out hold after clk hi
CONSTANT tDC_arr : DevTimeArr := (2.0 ns, 2.0 ns); --min
-- clk hi to out hi Z
CONSTANT tCKHZ_arr : DevTimeArr := (5.5 ns, 6.0 ns); -- max
-- clk hi to out lo Z
CONSTANT tCKLZ_arr : DevTimeArr := (0.1 ns, 0.1 ns); -- min
-- port to port del
CONSTANT tCCS_arr : DevTimeArr := (5.0 ns, 6.0 ns); -- min
END ;
224 Глава 7. Функциональная модель микросхемы двухпортовой памяти
7.4.4. Модуль контроля временных параметров
-- File name : dual_port_ramv_timing_check.vhd
------------------------------------------------------------
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; USE ieee.vital_timing.ALL;
USE work.dual_port_ramv_timing_data.ALL;
ENTITY dual_port_ramv_timing_check IS
GENERIC (
----------------------------------------------------------------
--non -VITAL generics
----------------------------------------------------------------
Device_Type :MaxFreqVal :=f83;
data_length : INTEGER :=36;
addr_length : INTEGER :=18;
-- timing check control parameters
InstancePath : STRING := " UAT " ;
partID : String := "dual_port_ramv.vhdl ";
TimingChecksOn : BOOLEAN := TRUE ;--:= DefaultTimingChecks;
MsgOn : BOOLEAN := TRUE ;--:= DefaultMsgOn;
XOn : BOOLEAN := TRUE --:= DefaultXOn;
);
-------------------PORT DECLARATION -----------------PORT (
AL : IN std_logic_vector(addr_length-1 DOWNTO 0);
AR : IN std_logic_vector(addr_length-1 DOWNTO 0);
RWL : IN std_logic ;
RWR : IN std_logic ; OEL_n : IN std_logic ;
OER_n : IN std_logic ;
IOL : IN std_logic_vector(data_length-1 DOWNTO 0);
IOR : IN std_logic_vector(data_length-1 DOWNTO 0);
CLKL : IN std_logic ; CLKR : IN std_logic ;
CE0L_n: IN std_logic ; CE1l : IN std_logic ;
CE0R_n: IN std_logic ; CE1R : IN std_logic ;
tx_viol: OUT std_logic ; ty_viol: OUT std_logic
);
END ;
----*****************************************************
ARCHITECTURE vhdl_behavioral of dual_port_ramv_timing_check IS
-- clock times
CONSTANT tCYC2:TIME:= tCYC2_arr(DEVICE_TYPE);--- (10 ns, 12 ns); --min
CONSTANT tCH2:TIME:= tCH2_arr(DEVICE_TYPE); -- ( 3.5 ns,4.0 ns ); -- min
CONSTANT tCL2:TIME:= tCL2_arr(DEVICE_TYPE);-- ( 3.5 ns,4.0 ns ); -- min
CONSTANT tR :TIME:= tR_arr(DEVICE_TYPE);
CONSTANT tF :TIME:= tF_arr(DEVICE_TYPE);
--SETUP -HOLD TIMES--------CONSTANT tSA:TIME:= tSA_arr(DEVICE_TYPE); -- -- min
CONSTANT tSC:TIME:= tSC_arr(DEVICE_TYPE); -- -- min
CONSTANT tSW:TIME:= tSW_arr(DEVICE_TYPE); -- -- min
CONSTANT tSD:TIME:= tSA_arr(DEVICE_TYPE); -- -- min
--HOLD ---------------CONSTANT tHA:TIME:= tHA_arr(DEVICE_TYPE); -- min
CONSTANT tHC:TIME:= tHC_arr(DEVICE_TYPE); -- min
Глава 7. Функциональная модель микросхемы двухпортовой памяти 225
CONSTANT thW:TIME:= tHW_arr(DEVICE_TYPE); -- min
CONSTANT tHD:TIME:= tHA_arr(DEVICE_TYPE); -- min
--OUTPUT DELAY TIMES---CONSTANT tOE:TIME := tOE_arr(DEVICE_TYPE); --max
CONSTANT tOLZ:TIME:= tOLZ_arr(DEVICE_TYPE); -- min
CONSTANT tOHZ:TIME:= tOHZ_arr(DEVICE_TYPE); -- min
CONSTANT tCD2:TIME:= tCD2_arr(DEVICE_TYPE); -- max
CONSTANT tDC:TIME := tDC_arr(DEVICE_TYPE); -- max
CONSTANT tCKHZ:TIME:= tCKHZ_arr(DEVICE_TYPE); --- min
CONSTANT tCKLZ:TIME:= tCKLZ_arr(DEVICE_TYPE); --- max
CONSTANT tCCS:TIME:= tCCS_arr(DEVICE_TYPE); -- -- min
---END OF CONTANT DELAY SECTION------------------------------
-------additional signals for use in the CHIP select check and delay proc
signal cel_n,cer_n:std_logic:='0';
-------------------------------------------------------------
--ВЫЗЫВАЕМЫЕ VITAL-ПРОЦЕДУРЫ
---------------------------------------------------------BEGIN
-- ВЫЧИСЛЕНИЕ ПРОМЕЖУТОЧНЫХ СИГНАЛОВ
cel_n<= '0' when( CE0L_n='0') AND ( CE1l='1') else '1';
--выбор кристалла- cel_n -левый порт
cer_n<= '0' when ( CE0R_n='0') AND ( CE1R='1') else '1';
-- Timing Check Section
TimingChecks: PROCESS ( AL, AR, CLKL, CLKR, OEL_n , OER_n ,
cel_n,cer_n, -- chip select
RWL,RWR, IOL , IOR
)
-- Timing Check Variables
-- Pulse Width Check Variables
VARIABLE Pviol_CLKL : X01 := '0';
VARIABLE PD_CLKL : VitalPeriodDataType
:= VitalPeriodDataInit;
VARIABLE Pviol_CLKR : X01 := '0';
VARIABLE PD_CLKR : VitalPeriodDataType
:= VitalPeriodDataInit;
VARIABLE Pviol_OEL_n : X01 := '0';
VARIABLE PD_OEL_n : VitalPeriodDataType
:= VitalPeriodDataInit;
VARIABLE Pviol_OER_n : X01 := '0';
VARIABLE PD_OER_n : VitalPeriodDataType
:= VitalPeriodDataInit;
-- Setup/Hold Check Variables
VARIABLE Tviol_AL_CLKL : X01 := '0'; --------L
VARIABLE TD_AL_CLKL : VitalTimingDataType;
VARIABLE TViol_AR_CLKR : X01 := '0'; -------R
VARIABLE TD_AR_CLKR : VitalTimingDataType;
---------------------------------------------------------
----RWL
VARIABLE Tviol_RWL_CLKL : X01 := '0'; --------A
VARIABLE TD_RWL_CLKL : VitalTimingDataType;
----RWR
VARIABLE Tviol_RWR_CLKR : X01 := '0'; ------B
VARIABLE TD_RWR_CLKR : VitalTimingDataType;
226 Глава 7. Функциональная модель микросхемы двухпортовой памяти
---------------------------------------------------------
-- CHIP ENABLE
VARIABLE Tviol_cel_n_CLKL : X01 := '0';------------L
VARIABLE TD_cel_n_CLKL : VitalTimingDataType;
VARIABLE Tviol_cer_n_CLKR : X01 := '0'; ------------R
VARIABLE TD_cer_n_CLKR : VitalTimingDataType;
--------------------------------------------------------------
-- IO DATA--VARIABLE Tviol_IOL_CLKL : X01 := '0';--------A
VARIABLE TD_IOL_CLKL : VitalTimingDataType;
VARIABLE Tviol_IOR_CLKR : X01 := '0'; ------------B
VARIABLE TD_IOR_CLKR : VitalTimingDataType;
----------------------------------------------------------
-- Violation variable (used to OR all individual violation variables)
VARIABLE XViolation , YViolation : X01 := '0';
BEGIN
--Проверки временных соотношений- только левый порт-
-- правый по аналогии с измененными именами – буква l на r
IF (TimingChecksOn)
THEN
-- CLKL period and pulse width check(high & low)
VitalPeriodPulseCheck (
TestSignal => CLKL, TestSignalName => "CLKL",
Period => tCYC2, PulseWidthHigh => tCH2,
PulseWidthLow => tCL2,
CheckEnabled => (cel_n = '0'),--TRUE,
HeaderMsg => InstancePath & partID,
PeriodData => PD_CLKL,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_CLKL);
-- OE pulse width check(high )
VitalPeriodPulseCheck (
TestSignal => OEL_n,
TestSignalName => "OEL_n",
Period => tOHZ+tOLZ,
PulseWidthHigh => tOHZ,
PulseWidthLow => tOLZ,
CheckEnabled => TRUE,
HeaderMsg => InstancePath & partID,
PeriodData => PD_OEL_n,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_OEL_n);
------------------------------------
-- ADDRESS CHECK
-- AL/CLKL setup/hold time checks
VitalSetupHoldCheck (
TestSignal => AL,
TestSignalName => "AL",
RefSignal => CLKL,
RefSignalName => "CLKL",
Глава 7. Функциональная модель микросхемы двухпортовой памяти 227
SetupHigh => tSA,
SetupLow => tSA,
HoldHigh => thA,
HoldLow => thA,
CheckEnabled => (cel_n = '0'),
RefTransition => '/',
HeaderMsg => InstancePath & partID,
TimingData => TD_AL_CLKL,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_AL_CLKL);
-- RWL/CLKL setup/hold time check
VitalSetupHoldCheck (
TestSignal => RWL,
TestSignalName => "RWL",
RefSignal => CLKL,
RefSignalName => "CLKL",
SetupHigh => tSW,
SetupLow => tSW,
HoldHigh => thW,
HoldLow => thW,
CheckEnabled => (cel_n = '0'),--True,
RefTransition => '/',
HeaderMsg => InstancePath & partID,
TimingData => TD_RWL_CLKL,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RWL_CLKL);
--------------CHIP ENABLE CHECK -----------------------
-- cel_n/CLKL setup/hold time check
VitalSetupHoldCheck (
TestSignal => cel_n,
TestSignalName => "cel_n= not(not CE0L_n and CE1l) ",
RefSignal => CLKL,
RefSignalName => "CLKL",
SetupHigh => tSC,
SetupLow => tSC,
HoldHigh => thC,
HoldLow => thc,
CheckEnabled => True,
RefTransition => '/',
HeaderMsg => InstancePath & partID,
TimingData => TD_cel_n_CLKL,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_cel_n_CLKL);
-- IOL/CLKL setup/hold time check
VitalSetupHoldCheck (
TestSignal => IOL,
TestSignalName => "IOL",
RefSignal => CLKL,
RefSignalName => "CLKL",
SetupHigh => tSD,
228 Глава 7. Функциональная модель микросхемы двухпортовой памяти
SetupLow => tSD,
HoldHigh => thD,
HoldLow => thd,
CheckEnabled => (cel_n = '0') AND (RWL = '0'),--WRITE
--True,
RefTransition => '/',
HeaderMsg => InstancePath & partID,
TimingData => TD_IOL_CLKL,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_IOL_CLKL);
XViolation := Pviol_CLKL OR Pviol_OEL_n OR
Tviol_RWL_CLKL OR Tviol_cel_n_CLKL OR
Tviol_IOL_CLKL OR Tviol_AL_CLKL ;
YViolation :=
Pviol_CLKR OR
Pviol_OER_n OR
Tviol_RWR_CLKR OR
Tviol_cer_n_CLKR OR
Tviol_IOR_CLKR OR
Tviol_AR_CLKR
;
tx_viol<= XViolation;
ty_viol<= YViolation;
END IF;
END PROCESS TimingChecks;
END ;
7.4.5. Пакет функций преобразования типов данных
LIBRARY ieee; USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;
USE STD.TEXTIO.all; USE ieee.std_logic_textio.ALL;
PACKAGE mem_pac is
CONSTANT MEM_WARNINGS_ON: BOOLEAN:=TRUE;
-- when false, no warning msg about
-- u or x bit in the addr val
TYPE biginteger is RECORD
lowbit:INTEGER; higbit:INTEGER;
END RECORD;
procedure print_msg (text:IN STRING; data:IN std_logic_vector;
addr: IN STD_LOGIC_VECTOR);
procedure print_addrmsg (text:IN STRING;
addr: IN STD_LOGIC_VECTOR);
function address_trans (ARG:IN std_logic_vector) return NATURAL ;
function std_memdata_to_bit ( s: IN std_logic_vector
)return bit_VECTOR;
--RESULT size need to be 1 bit more that size s !!!
function bit_memdata_to_std ( s: IN bit_vector
)return std_logic_vector;
--result size need to be 1 bit less that s !!!
function std_memdata_to_biginteger ( ARG: IN std_logic_vector
)return biginteger;
Глава 7. Функциональная модель микросхемы двухпортовой памяти 229
--RESULT sign=1 means X value
function std_memdata_to_integer (ARG: IN std_logic_vector
)return integer;
--RESULT sign=1 means X value
function biginteger_memdata_to_std ( data: IN biginteger;
Constant size : IN NATURAL
)return std_logic_vector;
--result when <0 need to be all X !!!
function integer_memdata_to_std ( --result when <0 need be all bit= X !!!
data: IN integer;
Constant size : IN NATURAL
) return std_logic_vector ;
end MEM_PAC;
----------------------------------------------------------------PACKAGE BODY mem_pac is
PROCEDURE print_msg (text:IN STRING; data:IN std_logic_vector;
addr: IN STD_LOGIC_VECTOR)is
VARIABLE msg:line;
BEGIN
Write (msg,String'("**CHIP MSG **"));
Write (msg,String'("Time:"));Write (msg, Now);
Write (msg, text );Write (msg,String'(" data ="));
hwrite (msg,data); Write (msg,String'(" addr ="));
hwrite (msg, "00"& addr );--for HWRITE need to
-- have vector with an odd ( multiple of 4)length
Writeline(output,msg);
END;
PROCEDURE print_addrmsg (text:IN STRING;
addr: IN STD_LOGIC_VECTOR)is
VARIABLE msg:line;
BEGIN
Write (msg,String'("***CHIP MSG **"));
Write (msg,String'("Time:"));Write (msg, Now);
Write (msg, text ); Write (msg,String'(" addr ="));
hwrite (msg, "00"& addr );--for HWRITE need to
-- have vector with an odd ( multiple of 4)length
Writeline(output,msg);
END;
------------------------------------------------------------------
function address_trans (ARG:IN std_logic_vector
) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: std_logic_vector(ARG_LEFT DOWNTO 0) is ARG;
variable XARG: std_logic_vector (ARG_LEFT DOWNTO 0);
variable RESULT: NATURAL := 0;
Variable uonce : BOOLEAN := TRUE;
Variable xonce : BOOLEAN := TRUE;
variable TMP:STD_ULOGIC:='0';
begin
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
TMP:=XXARG(I);
if TMP = '1' then
230 Глава 7. Функциональная модель микросхемы двухпортовой памяти
RESULT := RESULT + 1;
elsif (TMP = 'U'and MEM_WARNINGS_ON and uonce)THEN
uonce := FALSE;
assert FALSE
report "Address vector containsaU-itisbeing mapped to:0 "
severity WARNING;
elsif (TMP = 'X'and MEM_WARNINGS_ON and xonce) then
xonce := FALSE;
assert false
report "Address vector contains anX-itisbeing mapped to:0 "
severity WARNING;
end if;
end loop;
return RESULT;
end address_trans;
-----------------------------function std_memdata_to_integer
( ARG: IN std_logic_vector ) return integer
--RESULT <0 means X value of data word
is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: std_logic_vector(ARG_LEFT DOWNTO 0) is ARG;
variable XARG: std_logic_vector (ARG_LEFT DOWNTO 0);
variable RESULT: integer := 0;
Variable uonce : BOOLEAN := TRUE;
Variable xonce : BOOLEAN := TRUE;
variable TMP:STD_ULOGIC:='0';
begin
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
TMP:=XXARG(I);
if TMP = '1' then
RESULT := RESULT + 1;
elsif (TMP = 'U'and MEM_WARNINGS_ON and uonce)THEN
uonce := FALSE;
assert FALSE
report "Data vector contains a U “ &
“- it is being mapped to all:X "
severity WARNING;
RESULT :=-RESULT;
EXIT;
elsif (TMP = 'X'and MEM_WARNINGS_ON and xonce) then
xonce := FALSE;
assert false
report "Data vector contains an X - mapped to all:X "
severity WARNING;
RESULT :=-RESULT;
EXIT;
end if;
end loop;
return RESULT;
end ; -- std_memdata_to_integer;
------------------------------------------------------------------
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