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voltage is applied to its respective terminal while the other terminal is
grounded (for example, +5 V and ground or –5 V and ground). Having both a
positive and negative power supply voltage will allow the output signal to
swing positive and negative, above and below zero. As with all high gain
amplifiers, however, the output voltage can never exceed the value of the +V
and –V supply voltages.
+V
cc
power supply
inverting
input
output
noninverting
input
-V
cc
+V
cc
V
cc1
V
>0
out
(b) (c)
Fig. 9.2. Power supply connections:
(b) and (c) single supply voltage
V
cc1
V
cc2
(a)
V
<0
out
-V
cc
(a) dual supply voltages;
V
cc2
Op-Amp Packages
The entire op-amp circuit is placed within one of two basic packages,
shown in fig. 9.3. The TO-5 metal can package is available with 8, 10, or 12
leads, while the dual in-line through-hole and surface-mount packages
typically have 8 or 14 pins.
1
2
3
4
Fig. 9.3. Op-amp packages
91
LM
311
CN
Top v ie w
8
7
6
5
Like all ICs, an identification code is used to indicate the device
manufacturer, device type, and key characteristics. For example, the
‘MC741N’ code indicates that the 741 op-amp is made by Motorola, it is
designed for commercial application in which the temperature range is
between 0 to 70 °C, and the package is a through-hole DIP with longer leads.
Referring back to the IC packages, you can see that in addition to these two
inputs, single output, and two power supply terminals, there are two additional
leads labeled offset. These two inputs are commonly connected to a
potentiometer that can be adjusted to set the output at zero volts when both
inverting and noninverting inputs are at zero volts. Balancing the op-amp in this
way is generally needed due to imbalances within the op-amp’s internal circuit.
9.1.1. General Properties of Op-Amps
As it has been mentioned previously, the operational amplifier contains
three amplifier circuits, and these three circuits are all interconnected and
contained within a single IC. Referring to the block diagram of the op-amp in
fig. 9.4 you can see that these three circuits are a differential amplifier, a
voltage amplifier, and an output amplifier. Combined, these three circuits
give the op-amp its key characteristics, which are the high gain, high input
impedance, and low output impedance. We will briefly review their
characteristics because, when combined, they determine the characteristics of
the op-amp.
The Differential Amplifier within the Op-Amp
The differential amplifier within the op-amp is connected to operate in its
‘differential-input, single-output mode’. When both input signals are equal in
amplitude and in phase with one another, they are referred to as common-
mode input signals. On the other hand, if the input signals are out of phase
with one another, they are referred to as differential-mode input signals. The
differential amplifier will amplify differential input signals and reject
common-mode input signals. The questions are what are common-mode input
signals and why do we need to reject them? The answers are the following:
temperature changes and noise are common-mode input signals, and they are
unwanted signals. Consider these common-mode signals in detail.
1. Temperature variations within the electronic equipment affect the
operation of semiconductor materials and, therefore, the operation of
semiconductor devices. These temperature variations can cause the d.c.
output voltage of the first stage to drift away from its normal Q point. The
second-stage amplifier amplifies this voltage change in the same way as any
d.c. input signal does and this occurs at all of the following amplifier stages.
92
The increase or decrease in the normal Q-point bias for all the amplifier
A
A
A
A
stages will make this bias progressively worse due to this thermal instability.
The final stage may have a Q point that is so far from its mid position that an
input signal may drive it into saturation or cutoff, causing a signal distortion.
With the differential amplifier, any change that occurs due to temperature
changes affects both stages and so it does not appear at the output of the
differential amplifier, due to its common-mode rejection.
2. The second common-mode input signal that the differential
amplifier removes is noise. It is often necessary to amplify low-level signals
from low-sensitivity sources such as microphones, light detectors, and other
transducers. High-gain amplifiers are used to increase the amplitude of these
small input signals up to a more usable level that is large enough to drive or
control a load, such as a loudspeaker. The 60 Hz a.c. power line, or any other
electrical variation, can induce a noise signal along with the input signal at
the input of this high-gain amplifier. Since these noise signals are induced at
all points in the circuit, and are identical in the amplitude and the phase, the
differential amplifier blocks these unwanted signals because they are present
at both inputs of the differential amplifier (in this case noise is a commonmode input). A true input signal, on the other hand, appears at the two inputs
of the differential amplifier as a differential input signal, and therefore is
amplified.
Common-Mode Rejection Ratio
A differential input signal is amplified by the op-amp’s differential
amplifier and passed to the output, while unwanted signals caused by
temperature variations or noise appear as common-mode input signals and
therefore are rejected. An op-amp’s ability to provide a high
gain (А
) and a low common-mode gain (ACM) is directly dependent on its
VD
differential
internal differential amplifier and is a measure of an op-amp’s performance.
This ratio is called the
common-mode rejection ratio (CMRR) and is
calculated with the following formula
CMMR
Looking at this formula, you can see that the higher the A
gain), or the smaller the A
(common-mode gain), the higher the CMRR
CM
VD
.
CM
(differential
VD
value, and therefore a better the operational amplifier. This ratio can also be
expressed in dBs by using the following formula:
CMMR
20log
93
VD
, dB.
CM
EXAMPLE
If an op-amp’s differential amplifier has a differential gain of 5,000 and
a common-mode gain of 0.5, what is the operational amplifier’s CMRR?
Express the answer in standard gain and dBs.
Solution:
5000
0.5
10000;
dB.
CMMR
A
CMMR
20log 20log10000 20 4 80
VD
A
CM
A
VD
A
CM
A CMRR of 10,000 or 80 dB means that the op-amp’s desired input
signals are amplified 10,000 times more than the unwanted common-mode
input signals.
The Op-Amp Block Diagram
Now let us turn to the op-amp block diagram in fig. 9.4. It is the opamp’s differential-amplifier stage that provides the good common-mode
rejection and high differential gain.
offset
+V
null
cc
inverting
input
Differential
Amplifier
Voltage
Amplifier
Output
Amplifier
output
noninverting
input
R
load
offset
null
Fig. 9.4. Op-amp block diagram
-V
cc
As the op-amp’s ‘–’ and ‘+’ inputs are applied to either base of the diffamp, we know that input current is very small. It is this circuit characteristic
that provides the op-amp with another key feature, which is a high input
impedance. The voltage-amplifier stage following the diff-amp usually
consists of several Darlington-pair stages that provide an overall op-amp
voltage gain, typically 50,000 to 200,000. The output stage consists of a
complementary emitter-follower stage to provide a low output impedance
and high current gain. Thus the op-amp can deliver up to several milliamps,
depending on the value of the load.
94
The Op-Amp Circuit Diagram
The complete internal circuit of a typical op-amp is shown in fig. 9.5.
With integrated circuits, it is better to have transistors function as resistors
wherever possible because they occupy less chip space than actual resistors.
That is why the circuit seems to contain many transistors that have their base
and collector leads connected. You may also have noticed that no coupling
capacitors have been used so that the op-amp can amplify both a.c. and
d.c. input signals. As usual, the inputs are shown on the left, output on the
right, and power is above and below. As discussed previously, the two
balancing, or offset null, inputs will normally be connected to an external
potentiometer that can be adjusted to set the output at zero volts when both
the inverting and noninverting inputs are at zero volts. Balancing of the opamp to find the zero-volt output point, or null, in this way is generally needed
due to slight imbalances within the op-amp’s internal circuit.
Fig. 9.5. Op-amp internal circuit
An important point to realize at this time is that the op-amp is a single
component. Understanding of the op-amp’s internal circuitry helps us better
understand the circuit’s normal input/output relationships and characteristics.
These operational characteristics are important if we are going to determine
whether a circuit malfunction is internal or external to the op-amp. However,
95
since it is impossible to repair any internal op-amp failures, we will not
concentrate on every detail of the op-amp’s internal circuit.
DA1
inputs
2
3
6
output
zero
offset
+V
1
NC
5
NC
-V
pin 8 - not connected
cc
cc
7
4
power
supply
Fig. 9.6. Op-amp representation
Practical Properties
According to the equivalent circuit of the op-amp (fig. 9.7) we can
describe its practical properties.
Open-Loop Voltage Gain A
The op-amp amplifies the difference between the voltage on the
noninverting (+) and inverting (–) terminals.
The term ‘open loop’ signifies that there is no external feedback
connection between the output and either of the inputs. A is defined as the ratio
of the change in output voltage to the change in differential input voltage
(at low frequencies), usually for a load resistance of no less than 2 k.
Note that 100,000 is typical for A.
V
1
+V
cc
Inverting
input
R
Noninverting
input
V
2
in
R
out
A(V2-V1)
-V
cc
Fig. 9.7. Equivalent circuit of an op-amp
96
V
out
R
load
Input Resistance Rin
The input resistance is the open incremental resistance between the two
input terminals, and is typically 2 M.
Sometimes manufacturers quote the resistance between inputs and
ground.
Output Resistance R
out
The open-loop output resistance is usually between 50 and 500 .
The typical value of output resistance is 75 .
At this stage we can see that fig. 9.7 is the representation of an op-amp
as a circuit element.
Input Offset Voltage Vos
When both inputs are connected to ground, i. e. both differential and
common mode inputs are zero, the output should be zero. In practice there
are mismatches in amplifier components and if there is a mismatch in the
input stage, the effect is amplified and leads to a significant output voltage.
The input offset voltage V
is the differential input voltage required to make
os
the output zero, and is typically 1 mV.
With some op-amps two voltage offset (or
offset null) terminals are
provided. A potentiometer is connected between them and the slider is tied to
the specified d.c. supply rail, as in fig. 9.8, then the potentiometer can be
adjusted to zero offset voltage.
DA1
inputs
FC
FC
+
-V
m
V
cc
cc
W
zero
offset
NC
10k
Fig. 9.8. ‘Zero Offset’ terminals connected to 10 k potentiometer and negative
supply rail to zero the offset voltage
Input Bias Current I
B
NC
Op-amps with bipolar input stages are biased for the linear operation by
having the quiescent base voltage at the ground voltage and the negative
common emitter point. By operating at extremely low quiescent current
values the base bias currents are low but they must be taken in consideration.
output
frequency
correction
power
97
The input bias current IB for an op-amp is defined as the average of the two
I
I
input currents with the inputs grounded, i. e.
I
12
I
BB
B
.
2
The typical value is 30 nA. For an op amp with an FET input stage, IB is
much less: 50 pA is quoted for a OPA131.
The input bias current has an
R
1M
s
I
B2
adverse effect when the resistance
of the source feeding the op amp is
V
V
=0
s
Fig. 9.9. An adverse effect of input bias
I
B1
current
large. For example, the noninverting
input is grounded and the inverting
input is connected to a source of
1 M resistance and of voltage V
momentarily at 0 V. Then a 30 nA
bias current generates a voltage of
S
30 mV on the noninverting input.
Input Offset Current I
os
The problem referred to in the last paragraph would not arise if both
inputs were connected to equal resistances (one of which could be a passive
I
resistor) as shown in fig. 9.10, provided that
12BB
. Then, using the same
values as before, each input would be at –30 mV and the differential input
would be zero. However, if they are unequal, there is a finite differential
input voltage. It is therefore necessary to specify the difference between the
bias currents, and this is the input offset current I
os
,
A typical value for I
III
is 10 % of IB.
os
R
s
V
s
R2=R
Fig. 9.10. Reducing of the effect of input currents
12OS B B
I
B2
I
B1
1
.
Both IB and Ios are usually measured with the output at 0 V but in
practice the output voltage has little effect.
98
Power Supply Rejection Ratio (PSRR)
PSRR is a measure of an op-amp’s ability to disregard changes in power
supply voltage. It is specified by the change in offset voltage V
for a 1 V
os
change in d.c. power supply and is usually expressed in V/V. A typical
value is 15 V/V.
Maximum Differential Input Voltage
This is the maximum value of differential input voltage
that can be applied without damaging the op-amp.
VV V
Maximum Common Mode Input Voltage
This is the maximum voltage that the two inputs can be raised above
ground potential before the op-amp becomes nonlinear.
Output Voltage Swing
Ideally this is equal to the difference between the two supply rail
voltages but in practice it is a few volts less.
Frequency Response
An op-amp with a high open-loop voltage gain gives us flexibility: the
amount of negative feed-back (NFB) can then be chosen to bring down the
gain, i. e. the closed-loop gain, to any value required.
The danger of using NFB in a high gain system is instability. This is not a
problem at low frequency because op-amps are d.c. coupled and therefore
there are no CR couplings to produce the phase shift which leads to instability.
At high frequency, the transistor performance at each amplifying stage causes
not only a reduced gain, but also a phase lag: at frequencies where the gain per
stage falls at 20 dB/decade (6 dB/octave), the phase lag approaches 90°.
With two stages, then, at frequencies where the phase lag approaches
180°, the gain is too low to cause instability but with three stages there is a
substantial gain, where the phase lag is 180° and the probability of the
oscillation increases with the amount of NFB applied.
Frequency Compensation
Some op amps (such as the LM 741) have internal CR networks which
are deliberately designed to reduce gain at high frequency (HF). The result is
that the open-loop gain has characteristic falling at 20 dB/decade until the
gain is unity (0 dB).
Some op amps (such as the LM 709) have external frequency
compensation terminals for connected components (usually capacitor).
Frequency compensation circuit you can see in the datasheet for each
operational amplifier. If there are no frequency compensation terminals, the
op-amp has an internal frequency compensation.
99
Bandwidth (BW)
All amplifiers have a finite bandwidth. To a first approximation, the opamp has the frequency response of an integrator with the gain. That is, the
gain of a typical op-amp is inversely proportional to the frequency and is
characterized by its gain–bandwidth product (GBWP), which is equal to the
frequency where the amplifiers gain becomes unity. For example, an op-amp
with a GBWP of 1 MHz would have a gain of 5 at 200 kHz, and a gain of 1
at 1 MHz. This dynamic response coupled with a very high d.c. gain of the
op-amp gives it the characteristics of a first-order low-pass filter with a very
high d.c. gain and a low cutoff frequency given by the GBWP divided by the
d.c. gain.
Slew Rate (SR)
The slew rate is the maximum rate of
V
the output voltage change, i. e.
dV
Slew rate
out
.
1V
in
dt
It is normally measured in response
to a large input voltage step and is,
therefore, usually associated with a low
closed-loop voltage gain.
1V
V
out
t
Usually the slew rate is 5 to 10 V/s.
The effect of the slew rate in
dV
out
response to an input voltage step is
illustrated in fig. 9.11.
With a sine wave input, the slew rate
limits a combination of the maximum
operating frequency and the output
dt t
Fig. 9.11. Slew rate effect
0.2
s
voltage amplitude.
9.1.2. Operational Amplifier Types
1. General Purpose
These devices are designed for a very wide range of applications. These
op-amps have limited bandwidth but very good stability (they are called
frequency compensated). Usually they are Low cost (<1 $/Package).
2. Precision
Input offset voltage V
< 500 V (A > 100 dB)
os
Input offset voltage drift < 1 V/C
100
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