PCI_22
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Revision 2.2 |
LOCK# |
s/t/s |
Lock indicates an atomic operation to a bridge that may |
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require multiple transactions to complete. When LOCK# is |
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asserted, non-exclusive transactions may proceed to a bridge |
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that is not currently locked. A grant to start a transaction on |
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PCI does not guarantee control of LOCK#. Control of |
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LOCK# is obtained under its own protocol in conjunction |
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with GNT#. It is possible for different agents to use PCI |
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while a single master retains ownership of LOCK#. Locked |
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transactions may be initiated only by host bridges, PCI-to-PCI |
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bridges, and expansion bus bridges. Refer to Appendix F for |
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details on the requirements of LOCK#. |
IDSEL |
in |
Initialization Device Select is used as a chip select during |
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configuration read and write transactions. |
DEVSEL# |
s/t/s |
Device Select, when actively driven, indicates the driving |
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device has decoded its address as the target of the current |
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access. As an input, DEVSEL# indicates whether any device |
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on the bus has been selected. |
2.2.4. Arbitration Pins (Bus Masters Only)
REQ# |
t/s |
Request indicates to the arbiter that this agent desires use of |
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the bus. This is a point-to-point signal. Every master has its |
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own REQ# which must be tri-stated while RST# is asserted. |
GNT# |
t/s |
Grant indicates to the agent that access to the bus has been |
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granted. This is a point-to-point signal. Every master has its |
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own GNT# which must be ignored while RST# is asserted. |
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4 REQ# is an input to the arbiter, and GNT# is an output.
11
Revision 2.2
2.2.5. Error Reporting Pins
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PERR# |
s/t/s |
Parity Error is only for the reporting of data parity errors |
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during all PCI transactions except a Special Cycle. The |
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PERR# pin is sustained tri-state and must be driven active |
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by the agent receiving data (when enabled) two clocks |
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following the data when a data parity error is detected. The |
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minimum duration of PERR# is one clock for each data |
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phase that a data parity error is detected. (If sequential data |
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phases each have a data parity error, the PERR# signal will |
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be asserted for more than a single clock.) PERR# must be |
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driven high for one clock before being tri-stated as with all |
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sustained tri-state signals. Refer to Section 3.7.4.1. for more |
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details. |
SERR# |
o/d |
System Error is for reporting address parity errors, data parity |
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errors on the Special Cycle command, or any other system |
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error where the result will be catastrophic. If an agent does |
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not want a non-maskable interrupt (NMI) to be generated, a |
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different reporting mechanism is required. SERR# is pure |
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open drain and is actively driven for a single PCI clock by the |
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agent reporting the error. The assertion of SERR# is |
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synchronous to the clock and meets the setup and hold times |
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of all bused signals. However, the restoring of SERR# to the |
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deasserted state is accomplished by a weak pullup (same |
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value as used for s/t/s) which is provided by the central |
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resource not by the signaling agent. This pullup may take two |
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to three clock periods to fully restore SERR#. The agent that |
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reports SERR# to the operating system does so anytime |
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SERR# is asserted. |
5 Some planar devices are granted exceptions (refer to Section 3.7.2. for details).
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Revision 2.2
2.2.6. Interrupt Pins (Optional)
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INTA# |
o/d |
Interrupt A is used to request an interrupt. |
INTB# |
o/d |
Interrupt B is used to request an interrupt and only has |
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meaning on a multi-function device. |
INTC# |
o/d |
Interrupt C is used to request an interrupt and only has |
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meaning on a multi-function device. |
INTD# |
o/d |
Interrupt D is used to request an interrupt and only has |
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meaning on a multi-function device. |
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6 When several independent functions are integrated into a single device, it will be referred to as a multifunction device. Each function on a multi-function device has its own configuration space.
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Revision 2.2
Implementation Note: Interrupt Routing
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Device Number |
Interrupt Pin on |
Interrupt Pin on |
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on Motherboard |
Device |
Motherboard |
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0, 4, 8, 12, |
INTA# |
IRQW |
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16, 20, 24, 28 |
INTB# |
IRQX |
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INTC# |
IRQY |
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INTD# |
IRQZ |
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1, 5, 9, 13, |
INTA# |
IRQX |
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17, 21, 25, 29 |
INTB# |
IRQY |
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INTC# |
IRQZ |
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INTD# |
IRQW |
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2, 6, 10, 14, |
INTA# |
IRQY |
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18, 22, 26, 30 |
INTB# |
IRQZ |
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INTC# |
IRQW |
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INTD# |
IRQX |
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3, 7, 11, 15, |
INTA# |
IRQZ |
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19, 23, 27, 31 |
INTB# |
IRQW |
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INTC# |
IRQX |
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INTD# |
IRQY |
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Revision 2.2 |
2.2.7. Additional Signals |
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PRSNT[1:2]# in |
The Present signals are not signals for a device, but are |
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provided by an add-in board. The Present signals indicate to |
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the motherboard whether an add-in board is physically |
present in the slot and, if one is present, the total power requirements of the board. These signals are required for add-in boards but are optional for motherboards. Refer to Section 4.4.1. for more details.
Implementation Note: PRSNT# Pins
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CLKRUN# |
in, o/d, |
Clock running is an optional signal used as an input for a |
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s/t/s |
device to determine the status of CLK and an open drain |
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output used by the device to request starting or speeding up |
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CLK. |
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CLKRUN# is a sustained tri-state signal used by the |
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central resource to request permission to stop or slow CLK. |
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The central resource is responsible for maintaining |
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CLKRUN# in the asserted state when CLK is running and |
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deasserts CLKRUN# to request permission to stop or slow |
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CLK. The central resource must provide the pullup for |
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CLKRUN#. |
Implementation Note: CLKRUN#
CLKRUN# LV DQ RSWLRQDO VLJQDO XVHG LQ WKH 3&, PRELOH HQYLURQPHQW DQG QRW GHILQHG IRU 
WKH FRQQHFWRU 'HWDLOV RI WKH CLKRUN# SURWRFRO DQG RWKHU PRELOH GHVLJQ 
FRQVLGHUDWLRQV DUH GLVFXVVHG LQ WKH 3&, 0RELOH 'HVLJQ *XLGH 
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Revision 2.2 |
M66EN |
in |
The 66MHZ_ENABLE pin indicates to a device whether the |
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bus segment is operating at 66 or 33 MHz. Refer to |
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Section 7.5.1. for details of this signal’s operation. |
PME# |
o/d |
The Power Management Event signal is an optional signal |
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that can be used by a device to request a change in the |
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device or system power state. The assertion and |
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deassertion of PME# is asynchronous to CLK. This signal |
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has additional electrical requirements over and above |
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standard open drain signals that allow it to be shared |
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between devices which are powered off and those which |
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are powered on. In general, this signal is bused between all |
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PCI connectors in a system, although certain |
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implementations may choose to pass separate buffered |
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copies of the signal to the system logic. |
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Devices must be enabled by software before asserting this |
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signal. Once asserted, the device must continue to drive |
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the signal low until software explicitly clears the condition |
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in the device. |
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The use of this pin is specified in the PCI Bus Power |
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Management Interface Specification. The system vendor |
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must provide a pull-up on this signal, if it allows the signal |
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to be used. System vendors that do not use this signal are |
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not required to bus it between connectors or provide pull- |
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ups on those pins. |
3.3Vaux |
in |
An optional 3.3 volt auxiliary power source delivers power |
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to the PCI add-in card for generation of power management |
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events when the main power to the card has been turned off |
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by software. |
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The use of this pin is specified in the PCI Bus Power |
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Management Interface Specification. |
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A system or add-in card that does not support PCI bus |
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power management must treat the 3.3Vaux pin as reserved. |
Implementation Note: PME# and 3.3Vaux
PME# DQG 3.3Vaux DUH RSWLRQDO VLJQDOV GHILQHG E\ WKH 3&, %XV 3RZHU 0DQDJHPHQW
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Revision 2.2
2.2.8. 64-Bit Bus Extension Pins (Optional)
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AD[63::32] |
t/s |
Address and Data are multiplexed on the same pins and |
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provide 32 additional bits. During an address phase (when |
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using the DAC command and when REQ64# is asserted), the |
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upper 32-bits of a 64-bit address are transferred; otherwise, |
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these bits are reserved7 but are stable and indeterminate. |
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During a data phase, an additional 32-bits of data are |
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transferred when a 64-bit transaction has been negotiated by |
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the assertion of REQ64# and ACK64#. |
C/BE[7::4]# |
t/s |
Bus Command and Byte Enables are multiplexed on the same |
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pins. During an address phase (when using the DAC |
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command and when REQ64# is asserted), the actual bus |
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command is transferred on C/BE[7::4]#; otherwise, these bits |
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are reserved and indeterminate. During a data phase, |
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C/BE[7::4]# are Byte Enables indicating which byte lanes |
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carry meaningful data when a 64-bit transaction has been |
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negotiated by the assertion of REQ64# and ACK64#. |
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C/BE[4]# applies to byte 4 and C/BE[7]# applies to byte 7. |
REQ64# |
s/t/s |
Request 64-bit Transfer, when asserted by the current bus |
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master, indicates it desires to transfer data using 64 bits. |
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REQ64# also has the same timing as FRAME#. REQ64# |
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also has meaning at the end of reset as described in Section |
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3.8.1. |
ACK64# |
s/t/s |
Acknowledge 64-bit Transfer, when actively driven by the |
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device that has positively decoded its address as the target of |
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the current access, indicates the target is willing to transfer |
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data using 64 bits. ACK64# has the same timing as |
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DEVSEL#. |
PAR64 |
t/s |
Parity Upper DWORD is the even8 parity bit that protects |
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AD[63::32] and C/BE[7::4]#. PAR64 must be valid one |
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clock after each address phase on any transaction in which |
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REQ64# is asserted. |
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PAR64 is stable and valid for 64-bit data phases one clock |
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after either IRDY# is asserted on a write transaction or |
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TRDY# is asserted on a read transaction. (PAR64 has the |
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same timing as AD[63::32] but delayed by one clock.) The |
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master drives PAR64 for address and write data phases; the |
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target drives PAR64 for read data phases. |
7Reserved means reserved for future use by the PCI SIG Steering Committee. Reserved bits must not be used by any device.
8The number of “1”s on AD[63::32], C/BE[7::4]#, and PAR64 equals an even number.
17
Revision 2.2
2.2.9. JTAG/Boundary Scan Pins (Optional)
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TCK |
in |
Test Clock is used to clock state information and test data into |
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and out of the device during operation of the TAP. |
TDI |
in |
Test Data Input is used to serially shift test data and test |
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instructions into the device during TAP operation. |
TDO |
out |
Test Output is used to serially shift test data and test |
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instructions out of the device during TAP operation. |
TMS |
in |
Test Mode Select is used to control the state of the TAP |
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controller in the device. |
TRST# |
in |
Test Reset provides an asynchronous initialization of the TAP |
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controller. This signal is optional in IEEE Standard 1149.1. |
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18
Revision 2.2
2.3. Sideband Signals
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Revision 2.2
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