2.2 C8051f020 System Overview
The Silicon Labs C8051F020 is a fully integrated mixed-signal System-on-a-Chip microcontroller available in a 100 pin TQFP package.
All analog and digital peripherals are enabled/ disabled and configured by user software. The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allows field upgrades of the 8051 firmware.
2.3 Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051 (Figure 1.2). There are two separate memory spaces: program memory and data memory. The CIP-51 memory organization is shown in Figure 2.4. Program and data memory share the same address space but are accessed via different instruction types.
PROGRAM/DATA MEMORY
The memory organisation of the CIP-51 System Controller is similar to that of a standard 8051
Program Memory
The C8051F020's program memory consists of 65536 bytes of FLASH, of which 512 bytes, from addresses OxFEOO to OxFFFF, are reserved for factory use. There is also a single 128 byte sector at address 0x10000 to 0x1007F (Scratchpad Memory), which is useful as a small table for software program constants.
Data Memory
The C8051F020 data memory has both internal and external address spaces. The internal data memory consists of 256 bytes of RAM. The Special Function Registers (SFR) are accessed anytime the direct addressing mode is used to access the upper 128 bytes of memory locations from 0x80 to OxFF, while the general purpose RAM are accessed when indirect addressing is used (refer to Chapter 3 for addressing modes). The first 32 bytes of the internal data memory are addressable as four banks of 8 general purpose registers, and the next 16 bytes are bit-addressable or byte-addressable.
The external data memory has a 64K address space, with an on-chip 4K byte RAM block. An external memory interface (EMIF) is used to access the external data memory. The EMIF is configured by programming the EMI0CN and EMI0CF SFRs. The external data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4K directed to on-chip, above 4K directed to EMIF). The EMIF is also capable of acting in multiplexed mode or non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit.
Stack
The programmer stack can be located anywhere in the 256 byte internal data memory. A reset initializes the stack pointer (SP) to location 0x07; therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the stack should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.
C8051F020 duplicates the SFRs of 8051 and implements additional SFRs used to configure and access the microcontroller sub-systems The SFRs provide control and data exchange with the C8051F020's resources and peripherals. The C8051F020 duplicates the SFRs found in a typical 8051 implementation as well as implements additional SFRs which are used to configure and access the sub-systems unique to the microcontroller. This allows the addition of new functionalities while retaining compatibility with the MCS-51™ instruction set. Table 2.3 lists the SFRs implemented in the CIP-51 microcontroller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to OxFF. The SFRs with addresses ending in 0x0 or 0x8 (e.g. PO, TCON, P1, SCON, IE etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided.