5 Input
4
OUTPUT
3
PCB
should
have
a
low
impedance
return
path
(or
ground)
to 2
the supply. Removing the ground plane from all layers in the 1 immediate area of the amplifier helps to reduce stray capacitan-
05069-028
ces. The signal routing should be short and direct in order to 0
minimize the parasitic inductance and capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and
outputs. Input traces should be kept as far apart as possible
–1
0 80 160 240 320 400 480 560 640 720 800 Time (ns)
Figure 22.Unity-Gain Input Overdrive Recovery
from the output traces to minimize coupling (crosstalk) though the board.
Rev. 0 | Page 11 of 16
AD8397
CAPACITIVE LOAD DRIVE
When driving capacitive loads, many high speed operational amplifiers exhibit peaking in their frequency response. In a
gain-of-two circuit, Figure 23 shows that the AD8397 can drive
5
390pF 470pF
0
capacitive loads up to 270 pF with only 3 dB of peaking. For –5
amplifiers with more limited capacitive load drive, a small series –10
270pF
330pF
GAIN (dB)
resistor
(RS)
is
generally
used
between
the
amplifier
output
and –15
the
capacitive
load
in
order
to
minimize
peaking
and
ensure
device stability. Figure 24 shows that the use of a 2.2 Ω series –20 resistor can further extend the capacitive load drive of the –25
AD8397 out to 470 pF, while keeping the frequency response –30 peaking to within 3 dB.
05069-030
–35
5
220pF
0
270pF –40 0.01
0.1 1 10 100
FREQUENCY (MHz)
–5
150pF
Figure 24. Capacitive Load Peaking with 2.2 Ω Series Resistor
–10
100pF
GAIN (dB)
–15
–20
–25
–30
05069-021
–35
–40
0.01 0.1 1 10 100
FREQUENCY (MHz)
Figure 23.Capacitive Load PeakingWithout SeriesResistor
Rev. 0 | Page 12 of 16
45°
0.10
45
AD8397
OUTLINE
DIMENSIONS
5.00
(0.1968)
4.80
(0.1890)
8 4.00 (0.1574)
3.80 (0.1497) 1
5
6.20 (0.2440)
4 5.80 (0.2284)
1.27 (0.0500) BSC
0.25 (0.0098)
1.75 (0.0688)
1.35 (0.0532)
0.50 (0.0196)
0.25 (0.0099)
0.10
(0.0040)