Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
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List of Tables (Continued) |
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Table |
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SECTION 1SECTION 1
SECTION 2SECTION 2
2-1 Program and Data Memory Select Encoding . . . . . . . . . . . . . . . . . . . . . . . .2-4
SECTION 3SECTION 3
3-1 Memory Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 3-2 DSP56002 Operating Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 3-3 Organization of EPROM Data Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10 3-4 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 3-5 Exception Priorities Within an IPL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
SECTION 4SECTION 4
4-1 Program and Data Memory Select Encoding . . . . . . . . . . . . . . . . . . . . . . . .4-7 4-2 Wait State Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13 4-3 BR and BG During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
SECTION 5SECTION 5
5-1 Host Registers after Reset–DSP CPU Side . . . . . . . . . . . . . . . . . . . . . . . . .5-18 5-2 HREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5-3 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24
5-4 HREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-25 5-5 Host Registers after Reset (Host Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 5-6 Port B Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32
SECTION 6SECTION 6
6-1 Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 6-2 SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-32 6-3a Asynchronous SCI Bit Rates for a 40-MHz Crystal. . . . . . . . . . . . . . . . . . . .6-36 6-3b Frequencies for Exact Asynchronous SCI Bit Rates. . . . . . . . . . . . . . . . . . .6-36 6-4a Synchronous SCI Bit Rates for a 32.768-MHz Crystal . . . . . . . . . . . . . . . . .6-37
6-4b Frequencies for Exact Synchronous SCI Bit Rates . . . . . . . . . . . . . . . . . . .6-37 6-5 Definition of SC0, SC1, SC2, and SCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 6-6 SSI Clock Sources, Inputs, and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 6-7 SSI Operation: Flag 0 and Rx Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 6-8 SSI Operation: Flag 1 and Rx Frame Sync. . . . . . . . . . . . . . . . . . . . . . . . . .6-83 6-9 SSI Operation: Tx and Rx Frame Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83 6-10 Number of Bits/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 6-11 Frame Sync Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-91 6-12 Mode and Pin Definition Table – Continuous Clock . . . . . . . . . . . . . . . . . . .6-101
6-13 Mode and Pin Definition Table – Gated Clock . . . . . . . . . . . . . . . . . . . . . . .6-102
6-14 SSI Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-103 6-15a SSI Bit Rates for a 40-MHz Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-15b SSI Bit Rates for a 39.936-MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-16 Crystal Frequencies Required for Codecs . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-17 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-112
SECTION 7SECTION 7
7-1 Timer/Event Counter Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
APPENDIX A A-1
MOTOROLA |
LIST of TABLES |
xix |
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For More Information On This Product, |
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Go to: www.freescale.com |
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Freescale Semiconductor, Inc.
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List of Tables (Continued) |
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APPENDIX B B-1
B-1 Interrupts Starting Addresses and Sources . . . . . . . . . . . . . . . . . . . . . . . . .B-4
B-2 Instruction Set Summary — Sheet 1 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Freescale Semiconductor, Inc.
xx |
LIST of TABLES |
MOTOROLA |
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For More Information On This Product, |
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Go to: www.freescale.com |
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
DSP56002 User’s Manual Trouble Report
DSP Applications Fax Number — (512) 891-4665
Dr. BuB Bulletin Board —891-DSP3 (8 data bits, no parity, 1 stop)
We welcome your comments and suggestions. They help us provide you with better product documentation. Please send your suggestions/corrections to the Fax number or Email address above or mail this completed form to:
Motorola Inc.
6501 Wm. Cannon Drive West
Austin, Texas 78735-8598
Attn: DSP Applications/Documentation
Mail Drop: OE314
1.Did you find errors in the manual? Please give page number and a description of each error.
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Freescale Semiconductor, Inc.
DSP56002 User’s Manual Trouble Report
2.Did you find the manual clear and easy to use? Please comment on specific sections that you feel need improvement.
3. What sections of this manual do you consider most important/least important?
For More Information On This Product,
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Freescale Semiconductor, Inc. |
Order this document by |
MOTOROLA |
DSP56002UMAD/AD |
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SEMICONDUCTOR |
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TECHNICAL DATA |
DSP56002 |
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Addendum to |
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24-bit Digital Signal Processor |
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User’s Manual |
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This document, containing changes, additional features, further explanations, and clarifications, is a supplement to the original document:
Freescale Semiconductor, Inc.
DSP56002UM/AD |
Rev. 1 |
User’s Manual DSP56002 |
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24-bit Digital Signal Processor |
Change the following:
Page 1-4, Section 1.2 - Insert after first group of bullets “PLL based clocking with wide input frequency range, wide range frequency multiplication (1 to 4096) and power saving clock divider (2i, i=0,...,15) to reduce clock noise”
Page 1-4, Section 1.2 - Replace “24 General Purpose I/O Pins” with “25 General Purpose I/O pins”
Page 1-6 - Replace with the following Figure 1-2.
Page 2-14, Section 2.5 - Insert “Reset disables the TIO pin and causes it to be three-stated.”
Page 3-11, Section 3.4.3, third sentence - Replace “Mode 0” with “Mode 2”.
Page 5-19, Figure 5-11 - Replace “X:FFE” in two places with “X:$FFE8” on top and “X:FFE9” on bottom.
Page 6-28, Program listing - Move: “MOVE |
(R0)+ ;and increment the packing pointer” |
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to after the JCS instruction. |
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Replace |
“RTI” |
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with |
“RTI X:” |
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Replace |
“FLAG |
MOVE |
A,(R3)+” |
with |
“FLAG |
MOVE |
A,X:(R3)+” |
Page 6-68, Section 6.3.9, third sentence - Replace “Bits CD11–CD0, SCP, and STIR in the SCCR work together to determine the time base.” with “Bits CD11–CD0 and SCP in the SCCR and the STIR bit in the SCR work together to determine the time base.”
Page 6-127, Section 6.4.7.2, second paragraph - Replace “MC15500” with “MC145500”.
Page 6-130, Figure 6-72 - Replace “MC1550x” with “MC14550x”.
Page 6-155, Figure 6-88 - Replace “MC15500” with “MC145500”.
Page B-11, Figure B-4 - Add programming description for IPR bits 16 and 17 (see Figure B-4 below).
Page B-25, Figure B-32 - Change CRB bits 2-4 description (see Figure B-32 below).
Page B-27, Figure B-34 - Change arrows pointing to Timer Enable bits 1 and 0 as shown in Figure B-34 below.
MOTOROLA INC., 1995
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
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Freescale |
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Figure 1-2 DSP56002 Block Diagram |
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2 DSP56002 User’s Manual Addendum MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
MOTOROLA DSP56002 User’s Manual Addendum 3
For More Information On This Product,
Go to: www.freescale.com
4
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DSP56002 |
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ManualUser’s |
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MOTOROLA
Freescale Semiconductor, Inc.
CENTRAL PROCESSOR
SSI IPL
SSL1 SSL0 |
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Reset = $000000 |
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* = Reserved, Program as zero |
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Figure B-4 Interrupt Priority Register (IPR)
.Inc Semiconductor, Freescale
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
MOTOROLA DSP56002 User’s Manual Addendum 5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
SSI |
Serial Control Direction Bits |
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= External Clock |
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Frame Sync Length 0 |
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Sync/Async Control |
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0 |
= Asynchronous 1 = Synchronous |
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Gated Clock Control |
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0 |
= Continuous Clock |
1 = Gated Clock |
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SSI Mode Select |
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0 |
= Normal |
1 = Network |
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Transmit Enable |
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0 |
= Disable |
1 = Enable |
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Output Flag x |
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If SYN = 1 and SCD1=1 |
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Receive Enable |
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OFx |
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SCx Pin |
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0 |
= Disable |
1 = Enable |
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Transmit Interrupt Enable |
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0 |
= Disable |
1 = Enable |
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Receive Interrupt Enable |
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0 |
= Disable |
1 = Enable |
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SSI |
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23 |
• • • 15 |
14 |
13 |
12 |
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11 10 9 8 |
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7 6 5 4 |
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3 2 1 0 |
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* |
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RIE |
TIE |
RE |
TE |
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MOD |
GCK |
SYN |
FSL1 |
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FSL0 |
SHFDSCKDSCD2 |
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SCD1SCD0 |
OF1 |
OF0 |
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Control Register B (CRB) |
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0 |
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X:$FFED Read/Write |
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Reset = $000000 |
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* = Reserved, |
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Program as zero |
|||
Figure B-32 SSI Control Register B (CRB)
6 DSP56002 User’s Manual Addendum MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
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Sheet 1 of 1 |
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TIMER |
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Timer Control Bits 3-5 (TC0 - TC2) |
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TC2 |
TC1 |
TC0 |
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TIO |
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Clock |
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Mode |
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0 |
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0 |
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0 |
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GPIO |
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Internal |
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Timer |
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0 |
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0 |
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1 |
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Output |
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Internal |
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Timer Pulse |
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Timer Enable Bit 0 |
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0 |
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1 |
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0 |
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Output |
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Internal |
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Timer Toggle |
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0 = Timer Disabled |
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0 |
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1 |
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1 |
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X |
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X |
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Undefined |
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1 = Timer Enabled |
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1 |
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0 |
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0 |
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Input |
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Internal |
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Input Width |
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1 |
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0 |
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1 |
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Input |
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Internal |
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Input Period |
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Timer Interrupt Enable Bit 1 |
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1 |
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1 |
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0 |
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Input |
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External |
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Standard Time Counter |
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0 = Interrupts Disabled |
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1 |
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1 |
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1 |
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Input |
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External |
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Event Counter |
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1 = Interrupts Enabled |
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GPIO Bit 6 |
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Inverter Bit 2 |
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0 = 0- to-1 transitions on TIO |
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0 = TIO is Timer IO |
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input decrement the counter |
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1 = TIO is GPIO if TC2-TC0 are clear |
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1 = 1-to-0 transitions on TIO |
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input decrement the counter |
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Timer Status Bit 7 |
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Data Input Bit 9 |
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or |
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0 = TCSR read, or timer interrupt |
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0 = Zero read on TIO pin |
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|
Timer pulse inverted before |
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1 = One read on TIO pin |
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serviced |
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it goes to TIO output |
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1 = Counter decremented to 0 |
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Data Output Bit 10 |
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Direction Bit 8 |
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0 =Zero written to TIO pin |
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0 = TIO pin is input |
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1 = One written to TIO pin |
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1 = TIO pin is output |
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Timer Control and |
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23 • • |
• 15 |
14 |
13 |
12 |
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11 10 |
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9 |
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8 |
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7 |
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6 5 |
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1 |
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0 |
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* |
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* |
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* |
* |
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* |
DO |
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DI |
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DIR |
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TS |
GPIO |
TC2 |
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TC1 |
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TC0 |
INV |
TIE |
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TE |
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Status Register (TCSR) |
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0 |
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0 |
0 |
0 |
0 |
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0 |
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X:$FFDE (Read/Write) |
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Reset = $000200 |
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* = Reserved, Program as zero |
|||||||||||||||||||
Figure B-34 Timer Control and Status Register (TCSR)
MOTOROLA DSP56002 User’s Manual Addendum 7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
OnCE is a trademark of Motorola, Inc.
All product and brand names appearing herein are trademarks or registered trademarks of their respective holders.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical”, must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and bare registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: |
Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. |
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, United Kingdom. |
|
JAPAN: |
Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. |
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MOTOROLA Freescale Semiconductor, Inc. |
Order this document by: |
SEMICONDUCTOR USER’S MANUAL ADDENDUM |
DSP56002UMAD2/D |
|
|
DSP56002
24-BIT DIGITAL SIGNAL PROCESSOR FAMILY
This document, containing changes, additional features, further explanations, and clarifications, is a second addendum to the original document listed below:
Document Name: |
DSP56002 User’s Manual |
Order Number: |
DSP56002UM/AD |
Revision: |
1 |
Change the following:
Page 5-43 - In the first paragraph after item l0, delete “The code shown in Figure 5-25 is an excerpt from the Host I/O Port Technical Bulletin (in-house document).” Change the next sentence so that it begins “The MAIN PROGRAM in Figure 5-25 initializes...”
Page 7-4 - Change “In Timer Modes 4 and 5” to read “In Timer Modes 4, 5 and 6” in the first line of the last paragraph.
Page 7-6 - In the second paragraph of section 7.4.4, change “...is given in Chapter 3” to “...is given in Section 7.5.”
Page 7-20 - In the fifth line of code, change the operand from “#$CF,MR” to #$FC,MR” for the ANDI instruction.
Page 7-21 - In the eleventh line of code in section 7.8.4, change the operand from “#$CF,MR” to #$FC,MR” for the ANDI instruction.
Page 7-22 - In the ninth line of code on the page, “#$CF,MR” to #$FC,MR” for the ANDI instruction.
Page B-3 - In Figure B-1, the Timer Count Register should be shown as 24 bits long instead of 16 bits long.
©1996 MOTOROLA, INC. |
For More Information On This Product, |
|
Go to: www.freescale.com |
||
|
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
OnCE, Motorola, and 
are registered trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
How to reach us: |
|
|
USA/Europe: |
Hong Kong: |
Japan: |
Motorola Literature Distribution |
Motorola Semiconductors H.K. Ltd. |
Nippon Motorola Ltd. |
P.O. Box 20912 |
8B Tai Ping Industrial Park |
Tatsumi-SPD-JLDC |
Phoenix, Arizona 85036 |
51 Ting Kok Road |
Toshikatsu Otsuki |
1 (800) 441-2447 |
Tai Po, N.T., Hong Kong |
6F Seibu-Butsuryu-Center |
|
852-2662928 |
3-14-2 Tatsumi Koto-Ku |
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|
Tokyo 135, Japan |
|
|
03-3521-8315 |
MFAX: |
Internet: |
|
RMFAX0@email.sps.mot.com |
http://motserv.indirect.com/dsp/DSPhome.html |
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TOUCHTONE (602) 244-6609 |
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|
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 1
INTRODUCTION TO THE DSP56002
Freescale Semiconductor, Inc.
MOTOROLA |
1 - 1 |
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION CONTENTS
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW. . . . . . . . . . . . . . . . 1-4 1.4 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Freescale Semiconductor, Inc.
1 - 2 INTRODUCTION TO THE DSP56002 MOTOROLA
For More Information On This Product, Go to: www.freescale.com