Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

SIGNAL DESCRIPTIONS

register, setting the chip’s operating mode. The chip also samples the PINIT pin and writes its information into the PEN bit of the PLL Control Register, and it samples the CKP pin to determine the polarity of the CKOUT signal. When the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal.

2.2.4Power and Clock

The power and clock signals are presented in the following paragraphs.

2.2.4.1Power (Vcc), Ground (GND)

There are six sets of power and ground pins: a set of eight (four power, four ground) for internal logic; a set of eight (three power, five ground) for the address bus output buffer; a set of nine (three power, six ground) for the data bus output buffer; a set of eleven (four power, seven ground) for ports B and C and for the OnCE; a set of one power and one ground for the PLL; and a set of one power and one ground for the CKOUT pin. Refer to the pin assignments in the Layout Practices section of the DSP56002 Technical Data Sheet (DSP56002/D).

2.2.4.2External Clock/Crystal Input (EXTAL)

The EXTAL input interfaces the internal crystal oscillator input to an external crystal or an external clock.

2.2.4.3Crystal Output (XTAL)

This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL should not be connected. It may be disabled through software control using the XTLD bit in the PLL control register.

2.2.5Host Interface

The following paragraphs discuss the host interface signals, which provide a convenient connection to another processor through Port B on the DSP56002.

2.2.5.1Host Data Bus (H0–H7)

This bidirectional data bus transfers data between the host processor and the DSP56002. It acts as an input unless HEN is asserted and HR/W is high, making H0–H7 become outputs and allowing the host processor to read DSP56002 data. It is high impedance when HEN is deasserted. H0–H7 can be programmed as general-purpose I/O pins (PB0–PB7)

2 - 8 DSP56002 PIN DESCRIPTIONS MOTOROLA

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

SIGNAL DESCRIPTIONS

when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset.

2.2.5.2Host Address (HA0–HA2)

These inputs provide the address selection for each host interface register. HA0–HA2 can be programmed as general-purpose I/O pins (PB8–PB10) when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset.

2.2.5.3Host Read/Write (HR/W)

This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W is stable when HEN is asserted. It can be programmed as a general-purpose I/O pin (PB11) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset.

2.2.5.4Host Enable (HEN)

This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56002 data. When HEN is asserted and HR/W is low, H0–H7 become inputs. When HEN is deasserted, host data is latched inside the DSP. Normally, a chip select signal derived from host address decoding and an enable clock are used to generate HEN. HEN can be programmed as a general-purpose I/O pin (PB12) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset.

2.2.5.5Host Request (HREQ)

This open-drain output signal is used by the host interface to request service from the host processor, DMA controller, or a simple external controller. HREQ can be programmed as a general-purpose I/O (not open-drain) pin (PB13) when the host interface is not being used.

2.2.5.6Host Acknowledge (HACK)

This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 Family processors. When the port is defined as the host interface and neither of the HACK pin’s two functions are being used, the user may program this input as a general-purpose I/O pin.

For more details about the programming options for this pin, see Section 5.3.4.6 Host Ac-

knowledge (HACK). This pin is configured as a GPIO input pin during hardware reset.

Note: HACK should always be pulled high when it is not in use.

MOTOROLA DSP56002 PIN DESCRIPTIONS 2 - 9

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SIGNAL DESCRIPTIONS

2.2.6Serial Communication Interface (SCI)

The following signals relate to the SCI. They are introduced briefly here and described in more detail in SECTION 6 - PORT C.

2.2.6.1Receive Data (RXD)

This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data is sampled on the positive or the negative edge of the receive clock, depending on how the SCI control register is programmed. RXD can be programmed as a general-purpose I/O pin (PC0) when it is not being used as an SCI pin, and it is configured as a GPIO input pin during hardware reset.

2.2.6.2Transmit Data (TXD)

This output transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the transmit clock. This output is stable on the positive or the negative edge of the transmit clock, depending on how the SCI control register is programmed. TXD can be programmed as a general-purpose I/O pin (PC1) when the SCI TXD function is not being used, and it is configured as a GPIO input pin during hardware reset.

2.2.6.3SCI Serial Clock (SCLK)

This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is transferred in the synchronous mode. SCLK can be programmed as a general-purpose I/O pin (PC2) when the SCI SCLK function is not being used, and it is configured as a GPIO input pin during hardware reset.

2.2.7Synchronous Serial Interface (SSI)

The SSI signals are presented in the following paragraphs.The SSI operating mode affects the definition and function of SSI control pins SC0, SC1, and SC2. They are introduced briefly here and are described in more detail in SECTION 6 - PORT C.

2.2.7.1Serial Clock Zero (SC0)

This bidirectional pin’s function is determined by whether the SCLK is in synchronous or asynchronous mode. In synchronous mode, this pin is used for serial flag I/O. In asynchronous mode, this pin receives clock I/O. SC0 can be programmed as a general-purpose

I/O pin (PC3) when the SSI SC0 function is not being used, and it is configured as a GPIO input pin during hardware reset.

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