Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

SIGNAL DESCRIPTIONS

example, during reset, all signals are three-stated. Without pull-up resistors, the BR and WT signals may become active, causing two or more memory chips to try to simultaneously drive the external bus, which can damage the memory chips. A pullup resistor in the 50K-ohm range should be sufficient. Also, for future enhancements, all reserved pins (see Section Figure 2-1) should be left unconnected.

2.2.1.1Address (A0–A15)

These three-state output pins specify the address for external program and data memory accesses. To minimize power dissipation, A0–A15 do not change state when external memory spaces are not being accessed.

2.2.1.2Data Bus (D0–D23)

These pins provide the bidirectional data bus for external program and data memory accesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted.

2.2.2Port A Bus Control

The Port A bus control signals are discussed in the following paragraphs. The bus control signals provide a means to connect additional bus masters (which may be additional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) through port A to the DSP56002. They are three-stated during reset and may require pull-up resistors to prevent erroneous operation.

2.2.2.1Program Memory Select (PS)

This three-state output is asserted only when external program memory is referenced (see Table 2-1).

Table 2-1 Program and Data Memory Select Encoding

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Freescale Semiconductor, Inc.

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SIGNAL DESCRIPTIONS

2.2.2.2Data Memory Select (DS)

This three-state output is asserted only when external data memory is referenced (see Table 2-1).

2.2.2.3X/Y Select (X/Y)

This three-state output selects which external data memory space (X or Y) is referenced by DS (see Table 2-1).

2.2.2.4Read Enable (RD)

This three-state output is asserted to read external memory on the data bus (D0–D23).

2.2.2.5Write Enable (WR)

This three-state output is asserted to write external memory on the data bus (D0–D23).

2.2.2.6Bus Needed (BN)

The BN output pin is asserted whenever the chip requires the external memory expansion port (Port A). During instruction cycles where the external bus is not required, BN is deasserted. If an external device has requested the bus by asserting the BR input and the DSP has granted the bus (by asserting BG), the DSP will continue processing as long as no external accesses are required. If an external access is required and the chip is not the bus master, it will stop processing and remain in wait states until bus ownership is returned. If the BN pin is asserted when the chip is not the bus master, this indicates that processing has stopped and the DSP is waiting to acquire bus ownership. An external arbiter may use this pin to help decide when to return bus ownership to the DSP.

Note: The BN pin cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signal BS.

During hardware reset, BN is deasserted.

2.2.2.7Bus Request (BR)

When the bus request input (BR) is asserted, the DSP56002 will always relinquish the bus to an external device such as a processor or DMA controller. The external device will become the new master of the external address and data buses while the DSP continues internal operations using internal memory spaces. When BR is deasserted, the DSP56002 will again assume bus mastership.

When BR is asserted, the DSP56002 will always release Port A, including A0–A15, D0– D23, and the bus control pins (PS, DS, X/Y, RD, WR, and BS) by placing them in the highimpedance state, after the execution of the current instruction has been completed.

Note: To prevent erroneous operation, the BR pin should be pulled up when it is not in use.

MOTOROLA DSP56002 PIN DESCRIPTIONS 2 - 5

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Freescale Semiconductor, Inc.

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SIGNAL DESCRIPTIONS

2.2.2.8Bus Grant (BG)

When this output is asserted, it signals to the external device that it has been granted the external bus (i.e. Port A has been three-stated).This output is deasserted during hardware reset.

2.2.2.9Bus Strobe (BS)

The BS output is asserted when the DSP accesses Port A. It acts as an early indication of the state of the external bus access by the DSP56002. It may also be used with the bus wait input, WT, to generate wait states, a feature which provides capabilities such as connecting asynchronous devices to the DSP, allowing devices with differing timing requirements to reside in the same memory space, allowing a bus arbiter to provide a fast multiprocessor bus access, and providing an alternative to the WAIT and STOP instructions to halt the DSP at a known program location and have a fast restart. This output is deasserted during hardware reset.

2.2.2.10Bus Wait (WT)

For as long as it is asserted by an external device, this input allows that device to force the DSP56002 to generate wait states. If WT is asserted when BS is asserted, wait states will be inserted into the current cycle (see the DSP56002 Technical Data Sheet

(DSP56002/D) for timing details.

2.2.3Interrupt and Mode Control

The interrupt and mode control pins select the chip’s operating mode as it comes out of hardware reset, and they receive interrupt requests from external sources.

2.2.3.1 Mode Select A/External Interrupt Request A (MODA/IRQA)/STOP Recovery

This input pin has three functions. It works with the MODB and MODC pins to select the chip’s operating mode, it receives an interrupt request from an external source, and it turns on the internal clock generator, causing the chip to recover from the stop processing state. Reset causes this input to act as MODA.

During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of MODA, MODB, and MODC and writes the information to the Operating Mode Register to set the chip’s operating mode. (Operating Modes are discussed in SECTION 3 MEMORY MODULES AND OPERATING MODES.) After the chip has left the reset state, the MODA pin automatically changes to external interrupt request IRQA.

IRQA receives external interrupt requests. It can be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall

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SIGNAL DESCRIPTIONS

time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases.

2.2.3.2Mode Select B/External Interrupt Request B (MODB/IRQB)

This input pin works with the MODA and MODC pins to select the chip’s operating mode, and it receives an interrupt request from an external source. Reset causes this input to act as MODB.

During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of the mode pins and writes the information to the Operating Mode Register, which sets the chip’s operating mode. After the chip has left the reset state, the MODB pin automatically changes to external interrupt request IRQB.

IRQB receives external interrupt requests. It can be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases.

2.2.3.3Mode Select C/Non-Maskable Interrupt Request (MODC/NMI)

This input pin works with the MODA and MODB pins to select the chip’s operating mode, and it receives an interrupt request from an external source. Reset causes this input to act as MODC.

During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of the mode pins and writes the information to the Operating Mode Register, which sets the chip’s operating mode. After the chip has left the reset state, the MODC pin automatically changes to a nonmaskable interrupt request (NMI) input.

The negative-edge triggered NMI receives nonmaskable interrupt requests. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases.

2.2.3.4Reset (RESET)

This Schmitt trigger input pin is used to reset the DSP56002. When RESET is asserted, the DSP56002 is initialized and placed in the reset state. When RESET is deasserted, the chip writes the mode pin (MODA, MODB, MODC) information to the operating mode

MOTOROLA DSP56002 PIN DESCRIPTIONS 2 - 7

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