
- •Одеський національний політехнічний університет
- •Міністерство освіти і науки України одеський національний політехнічний університет
- •Протокол № 8 від 24.03.09
- •Наука і техніка
- •Lesson 1
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •In; one; licenses; through; systems.
- •Lesson 2
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 3
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 4
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 5
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 6
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 7
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 8
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 9
- •After text activity
- •I. Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
- •Lesson 10
- •After text activity
- •Reading Exercises:
- •II. Speaking Exercises:
- •III. Writing exercises:
After text activity
I. Reading Exercises:
Exercise 1. Read and memorize using a dictionary:
CMOS process; formidable challenges; etch; gate dielectrics; shallow junctions; raised-source drains; couple products; node; leveraging device strain; drive current; daunt. |
Exercise 2. Answer the questions:
1) What are the fundamental electrical components of integrated circuits?
2) What are characteristics of transistors?
3) What kind of new materials will help drive leading-edge transistor technology?
4) How may future changes in the transistor structure involve new techniques?
Exercise 3. Match the left part with the right:
1. These issues demand |
a) transistors with gate lengths less than 40 nm. |
2. The higher quiescent currents of transistors at this scale will require |
b) in size for mare than 40 years. |
3. Transistors have been shrinking |
c) extremely strict process control. |
4. We face the formidable challenges of building |
d) extensive system expertise. |
Exercise 4. Open brackets choosing the right words:
The (highest(top)(level/standard) of (control/checking) in lithography and etch is (required/requested) to keep the characteristics of (milliard/billion) of these transistors consistent across an entire wafer.
II. Speaking Exercises:
Exercise 1. Describe node; etch; dielectrics; junction; drain; leverage; transistor using the suggested words and expressions as in example:
node a connecting point; at; which; several lines; come together. example: The node is a connecting point at which several lines come together. |
etch make; an etching; of; an impression; made; from; an etched plate. |
dielectrics a material; such; as; glass; or; porcelain; with; negligible; electrical; or; thermal; conductivity. |
junction an act; of; joining; or; adjoining; things; the place; where; two; o more; things; come together. |
drain a gradual; depletion; of; energy; or; resources; emptying; accomplished; by; draining. |
leverage mechanical advantage; gained; by; being; in; a position; to use; a lever. |
transistor a semiconductor; device; capable; of; amplification. |
Exercise 2. Ask questions to the given answers:
1) Question: _____________________________________ ?
Answer: Equivalent gate oxides of 1 nm or less will require new high dielectrics to replace traditional silicon oxides.
2) Question: ______________________________________________ ?
Answer: The electrical characteristics of deep-submicron transistors bring new challenges to design not only for process RD, but also at the system level.
3) Question: ______________________________________________ ?
Answer: While much of our RD is currently focused on implementing transistors at the 90-nm node we are also devoting resources to studying transistor design at 65 nm and beyond.