21.5.1 Frame composition

As with the DS1 D4 framing format, the CEPT PCM-30 frame structure is subject of CCITT Recommendation G.704. Each CEPT PCM-30 frame consists of 32 time slots to include 30 voice chan­nels, one alignment signal and one signalling channel. Time slots 1 to 15 and 17 to 31 are assigned to the 30 voice or data channels. This frame composition is depicted in Figure 21.7.

The frame alignment signal FAS (0011011) is transmitted in bit positions 2 to 8 of time slot 0 of every other frame. Bit position 1 carries the International bit, while frames not containing the frame alignment signal, i.e. the odd frames, are used to carry National and International signalling bits and alarm indication for loss of frame alignment. The loss of frame alignment alarm is announced by alarm bit A, which is the third bit of the odd. To avoid imitation of the frame alignment signal, bit 2 of the odd frames is set to 1.

Time slot 16 in each CEPT 30 frame is used to transmit such signalling data as on-hook and off-hook conditions, dialling digits and call progress. Since a common channel is dedicated for the signalling data of all voice circuits, this method of signalling is referred to as common channel signalling. The signalling consists of four bits per channel, grouped in the two halves of time slot 16. It therefore requires 15 frames to carry the information of the 30 channels. Completed by a 16th frame (frame 0) they constitute a multiframe. Time slot 16 of this 16th frame contains a multiframe alignment pattern MAS which allows unambiguous numbering of the frames within the multiframe. Each channel thus arranges the signalling of 4 bits every 16 frames, i.e. every 2 milliseconds.

21.5.2 CRC-4 cyclic redundancy check

Where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of the frame, i.e. the International bit, is used for the 4-bit cyclic redun­dancy check described below.

Each CRC-4 multiframe, which is composed of 16 frames num­bered from 0 to 15, is divided into two 8 frame sub-multiframes or SMF, designated SMFI and SMFII which indicates their respective order of occurrence within the CRC-4 multiframe structure. The SMF is the Cyclic Redundancy Check-4 block size, i.e. 2048 bits.

In the frames containing the frame alignment signal, bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, referred to as Cl, C2, C3, and C4 in each SMF. In the frames not containing the frame alignment signal, bit 1 is used to to transmit the CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The CRC-4 multiframe alignment signal is a 7-bit sequence having the form 0011011. The E-bits are used to indicate received errored sub-multiframes by changing the binary state of one E-bit from 1 to 0 for each errored sub-mulnframe. Recommendation G.704 requires the delay between the detection of an errored sub-multiframe, and the setting of the E-bit that indicates the error state, to be less than 1 second. Table 21.3 shows the allocation of bits 1 to 8 of the frames for a complete CRC-4 multiframe.