Лабораторная работа 4 / FastChip / counter / counter

// Binding File - DO NOT EDIT
// Binding written December 7, 2006 10:23:58 AM MSK
// By FastChip Version 2.6.0 Build 030604-1706
// Binding last modified December 7, 2006 10:23:58 AM MSK
V 1 2;
D A7S20;
OP and_1.AND_WIDE4_0_0 15817;
OP and_1.AND_WIDE4_0_1 15945;
OP and_1.AND_WIDE4_0_2 16073;
OP and_1.AND_WIDE4_0_3 16201;
OP and_2.AND_WIDE4_0_0 16905;
OP and_2.AND_WIDE4_0_1 17033;
OP and_2.AND_WIDE4_0_2 17161;
OP and_2.AND_WIDE4_0_3 17289;
OP and_3.AND_WIDE4_0_0 15305;
OP and_3.AND_WIDE4_0_1 15433;
OP and_3.AND_WIDE4_0_2 15561;
OP and_3.AND_WIDE4_0_3 15689;
OP and_4.AND_WIDE4_0_0 13641;
OP and_4.AND_WIDE4_0_1 13769;
OP and_4.AND_WIDE4_0_2 13897;
OP and_4.AND_WIDE4_0_3 14025;
OP and_5.AND_WIDE4_0_0 12553;
OP and_5.AND_WIDE4_0_1 12681;
OP and_5.AND_WIDE4_0_2 12809;
OP and_5.AND_WIDE4_0_3 12937;
OP and_6.AND_WIDE4_0_0 17481;
OP and_6.AND_WIDE4_0_1 17609;
OP and_6.AND_WIDE4_0_2 17737;
OP and_6.AND_WIDE4_0_3 17865;
OP and_7.AND_WIDE4_0_0 20169;
OP and_7.AND_WIDE4_0_1 20297;
OP and_7.AND_WIDE4_0_2 20425;
OP and_7.AND_WIDE4_0_3 20553;
OP and_8.AND_WIDE4_0_0 19657;
OP and_8.AND_WIDE4_0_1 19785;
OP and_8.AND_WIDE4_0_2 19913;
OP and_8.AND_WIDE4_0_3 20041;
OP and_9.AND_WIDE4_0_0 20745;
OP and_9.AND_WIDE4_0_1 20873;
OP and_9.AND_WIDE4_0_2 21001;
OP and_9.AND_WIDE4_0_3 21129;
OP and_second.AND_WIDE4_0_0 19642;
OP and_third.AND_WIDE4_0_0 21146;
OP Inputs.0 4715;
OP Inputs.1 4720;
OP inv_1.inv_0 17274;
OP inv_2.inv_0 20154;
OP inv_2.inv_1 20026;
OP inv_2.inv_2 20393;
OP inv_7.inv_0 18297;
OP inv_7.inv_1 18074;
OP inv_7.inv_2 12489;
OP inv_7.inv_3 16457;
OP inv_and3.inv_0 17625;
OP inv_and3.inv_1 17449;
OP inv_and3.inv_2 17641;
OP inv_and3.inv_3 17849;
OP inv_and4.inv_0 14010;
OP inv_and4.inv_1 11722;
OP inv_and4.inv_2 12761;
OP inv_and4.inv_3 12826;
OP inv_and5.inv_0 17433;
OP inv_and5.inv_1 18090;
OP inv_and5.inv_2 12810;
OP inv_and5.inv_3 17769;
OP inv_and6.inv_0 17417;
OP inv_and6.inv_1 13962;
OP inv_and6.inv_2 13898;
OP inv_and6.inv_3 17785;
OP inv_and8.inv_0 19658;
OP inv_and8.inv_1 20953;
OP inv_and8.inv_2 20809;
OP inv_and8.inv_3 20969;
OP inv_and9.inv_3 20538;
OP or_1.AND_WIDE4_0_0 12041;
OP or_1.AND_WIDE4_0_1 12169;
OP or_1.AND_WIDE4_0_2 12297;
OP or_1.AND_WIDE4_0_3 12425;
OP or_2.AND_WIDE4_0_0 13129;
OP or_2.AND_WIDE4_0_1 13257;
OP or_2.AND_WIDE4_0_2 13385;
OP or_2.AND_WIDE4_0_3 13513;
OP Output_A.0 4661;
OP Output_A.1 4666;
OP Output_A.2 4553;
OP Output_A.3 4558;
P and_1.AND_WIDE4_0_0 Root.bank1_3.x3y0.lb.lutb;
P and_1.AND_WIDE4_0_1 Root.bank1_3.x2y0.lb.lutb;
P and_1.AND_WIDE4_0_2 Root.bank1_3.x1y0.lb.lutb;
P and_1.AND_WIDE4_0_3 Root.bank1_3.x0y0.lb.lutb;
P and_2.AND_WIDE4_0_0 Root.bank1_2.x3y0.lb.lutb;
P and_2.AND_WIDE4_0_1 Root.bank1_2.x2y0.lb.lutb;
P and_2.AND_WIDE4_0_2 Root.bank1_2.x1y0.lb.lutb;
P and_2.AND_WIDE4_0_3 Root.bank1_2.x0y0.lb.lutb;
P and_3.AND_WIDE4_0_0 Root.bank1_3.x7y0.lb.lutb;
P and_3.AND_WIDE4_0_1 Root.bank1_3.x6y0.lb.lutb;
P and_3.AND_WIDE4_0_2 Root.bank1_3.x5y0.lb.lutb;
P and_3.AND_WIDE4_0_3 Root.bank1_3.x4y0.lb.lutb;
P and_4.AND_WIDE4_0_0 Root.bank2_1.x3y0.lb.lutb;
P and_4.AND_WIDE4_0_1 Root.bank2_1.x2y0.lb.lutb;
P and_4.AND_WIDE4_0_2 Root.bank2_1.x1y0.lb.lutb;
P and_4.AND_WIDE4_0_3 Root.bank2_1.x0y0.lb.lutb;
P and_5.AND_WIDE4_0_0 Root.bank2_2.x3y0.lb.lutb;
P and_5.AND_WIDE4_0_1 Root.bank2_2.x2y0.lb.lutb;
P and_5.AND_WIDE4_0_2 Root.bank2_2.x1y0.lb.lutb;
P and_5.AND_WIDE4_0_3 Root.bank2_2.x0y0.lb.lutb;
P and_6.AND_WIDE4_0_0 Root.bank1_1.x7y0.lb.lutb;
P and_6.AND_WIDE4_0_1 Root.bank1_1.x6y0.lb.lutb;
P and_6.AND_WIDE4_0_2 Root.bank1_1.x5y0.lb.lutb;
P and_6.AND_WIDE4_0_3 Root.bank1_1.x4y0.lb.lutb;
P and_7.AND_WIDE4_0_0 Root.bank0_3.x3y0.lb.lutb;
P and_7.AND_WIDE4_0_1 Root.bank0_3.x2y0.lb.lutb;
P and_7.AND_WIDE4_0_2 Root.bank0_3.x1y0.lb.lutb;
P and_7.AND_WIDE4_0_3 Root.bank0_3.x0y0.lb.lutb;
P and_8.AND_WIDE4_0_0 Root.bank0_3.x7y0.lb.lutb;
P and_8.AND_WIDE4_0_1 Root.bank0_3.x6y0.lb.lutb;
P and_8.AND_WIDE4_0_2 Root.bank0_3.x5y0.lb.lutb;
P and_8.AND_WIDE4_0_3 Root.bank0_3.x4y0.lb.lutb;
P and_9.AND_WIDE4_0_0 Root.bank0_2.x7y0.lb.lutb;
P and_9.AND_WIDE4_0_1 Root.bank0_2.x6y0.lb.lutb;
P and_9.AND_WIDE4_0_2 Root.bank0_2.x5y0.lb.lutb;
P and_9.AND_WIDE4_0_3 Root.bank0_2.x4y0.lb.lutb;
P and_second.AND_WIDE4_0_0 Root.bank0_3.x7y1.lb.luta;
P and_third.AND_WIDE4_0_0 Root.bank0_2.x3y7.lb.luta;
P Inputs.0 Root.ionc3r34.iob.iocellb.pad;
P Inputs.1 Root.ionc3r34.iob.iocella.pad;
P inv_1.inv_0 Root.bank1_2.x0y1.lb.luta;
P inv_2.inv_0 Root.bank0_3.x3y1.lb.luta;
P inv_2.inv_1 Root.bank0_3.x4y1.lb.luta;
P inv_2.inv_2 Root.bank0_3.x1y2.lb.lutb;
P inv_7.inv_0 Root.bank1_1.x0y5.lb.lutb;
P inv_7.inv_1 Root.bank1_1.x2y3.lb.luta;
P inv_7.inv_2 Root.bank2_2.x3y4.lb.lutb;
P inv_7.inv_3 Root.bank1_2.x6y4.lb.lutb;
P inv_and3.inv_0 Root.bank1_1.x5y7.lb.lutb;
P inv_and3.inv_1 Root.bank1_1.x7y2.lb.lutb;
P inv_and3.inv_2 Root.bank1_1.x5y6.lb.lutb;
P inv_and3.inv_3 Root.bank1_1.x4y1.lb.lutb;
P inv_and4.inv_0 Root.bank2_1.x0y1.lb.luta;
P inv_and4.inv_1 Root.bank2_3.x1y0.lb.luta;
P inv_and4.inv_2 Root.bank2_2.x1y3.lb.lutb;
P inv_and4.inv_3 Root.bank2_2.x0y7.lb.luta;
P inv_and5.inv_0 Root.bank1_1.x7y3.lb.lutb;
P inv_and5.inv_1 Root.bank1_1.x2y2.lb.luta;
P inv_and5.inv_2 Root.bank2_2.x1y0.lb.luta;
P inv_and5.inv_3 Root.bank1_1.x4y6.lb.lutb;
P inv_and6.inv_0 Root.bank1_1.x7y4.lb.lutb;
P inv_and6.inv_1 Root.bank2_1.x0y4.lb.luta;
P inv_and6.inv_2 Root.bank2_1.x1y0.lb.luta;
P inv_and6.inv_3 Root.bank1_1.x4y5.lb.lutb;
P inv_and8.inv_0 Root.bank0_3.x7y0.lb.luta;
P inv_and8.inv_1 Root.bank0_2.x5y3.lb.lutb;
P inv_and8.inv_2 Root.bank0_2.x6y4.lb.lutb;
P inv_and8.inv_3 Root.bank0_2.x5y2.lb.lutb;
P inv_and9.inv_3 Root.bank0_3.x0y1.lb.luta;
P or_1.AND_WIDE4_0_0 Root.bank2_2.x7y0.lb.lutb;
P or_1.AND_WIDE4_0_1 Root.bank2_2.x6y0.lb.lutb;
P or_1.AND_WIDE4_0_2 Root.bank2_2.x5y0.lb.lutb;
P or_1.AND_WIDE4_0_3 Root.bank2_2.x4y0.lb.lutb;
P or_2.AND_WIDE4_0_0 Root.bank2_1.x7y0.lb.lutb;
P or_2.AND_WIDE4_0_1 Root.bank2_1.x6y0.lb.lutb;
P or_2.AND_WIDE4_0_2 Root.bank2_1.x5y0.lb.lutb;
P or_2.AND_WIDE4_0_3 Root.bank2_1.x4y0.lb.lutb;
P Output_A.0 Root.ionc4r34.iob.iocellb.pad;
P Output_A.1 Root.ionc4r34.iob.iocella.pad;
P Output_A.2 Root.ionc6r34.iob.iocellb.pad;
P Output_A.3 Root.ionc6r34.iob.iocella.pad;