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AT89C2051

14. Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol

 

 

Parameter

Min

Max

Units

 

 

 

 

 

 

 

VPP

 

 

Programming Enable Voltage

11.5

12.5

V

IPP

 

 

Programming Enable Current

 

250

µA

tDVGL

 

 

Data Setup to

 

 

 

 

 

 

 

 

 

Low

1.0

 

µs

PROG

 

tGHDX

 

 

Data Hold after

 

 

 

 

 

 

 

 

1.0

 

µs

PROG

 

tEHSH

 

 

P3.4

 

 

 

 

 

 

 

 

 

High to VPP

1.0

 

µs

(ENABLE)

 

tSHGL

 

 

VPP Setup to

 

 

 

 

 

 

 

Low

10

 

µs

PROG

 

tGHSL

 

 

VPP Hold after

 

 

 

 

 

 

 

 

 

 

10

 

µs

PROG

 

tGLGH

 

 

 

 

 

Width

1

110

µs

 

 

PROG

tELQV

 

 

 

 

 

 

Low to Data Valid

 

1.0

µs

 

 

ENABLE

 

tEHQZ

 

 

Data Float after

 

 

 

 

 

 

 

0

1.0

µs

 

 

ENABLE

tGHBL

 

 

 

 

 

High to

 

 

 

 

 

Low

 

50

ns

 

 

PROG

BUSY

 

tWC

 

 

Byte Write Cycle Time

 

2.0

ms

tBHIH

 

 

 

 

 

 

 

to Increment Clock Delay

1.0

 

µs

 

 

RDY/BSY\

 

tIHIL

 

 

Increment Clock High

200

 

ns

Note: 1.

Only used in 12-volt programming mode.

 

 

 

15. Flash Programming and Verification Waveforms

11

0368G–MICRO–6/05

16. Absolute Maximum Ratings*

.................................Operating Temperature

-55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

 

 

Maximum Ratings” may cause permanent dam-

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

 

 

functional operation of the device at these or any

Voltage on Any Pin

 

other conditions beyond those indicated in the

with Respect to Ground .....................................

-1.0V to +7.0V

operational sections of this specification is not

Maximum Operating Voltage

6.6V

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

DC Output Current

25.0 mA

reliability.

 

 

 

 

17. DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Max

Units

 

 

 

 

 

 

VIL

Input Low-voltage

 

-0.5

0.2 VCC - 0.1

V

VIH

Input High-voltage

(Except XTAL1, RST)

0.2 VCC + 0.9

VCC + 0.5

V

VIH1

Input High-voltage

(XTAL1, RST)

0.7 VCC

VCC + 0.5

V

VOL

Output Low-voltage(1)

IOL = 20 mA, VCC = 5V

 

0.5

V

(Ports 1, 3)

IOL = 10 mA, VCC = 2.7V

 

 

 

 

 

 

Output High-voltage

IOH = -80 µA, VCC = 5V ± 10%

2.4

 

V

 

 

 

 

 

VOH

IOH = -30 µA

0.75 VCC

 

V

(Ports 1, 3)

 

 

IOH = -12 µA

0.9 VCC

 

V

 

 

 

 

 

 

 

 

 

IIL

Logical 0 Input Current

VIN = 0.45V

 

-50

µA

(Ports 1, 3)

 

 

 

 

 

 

 

 

 

 

 

 

ITL

Logical 1 to 0 Transition Current

VIN = 2V, VCC = 5V ± 10%

 

-750

µA

(Ports 1, 3)

 

 

 

 

 

 

 

 

 

 

 

 

ILI

Input Leakage Current

0 < VIN < VCC

 

±10

µA

(Port P1.0, P1.1)

 

 

 

 

 

 

 

 

 

 

 

 

VOS

Comparator Input Offset Voltage

VCC = 5V

 

20

mV

VCM

Comparator Input Common

 

0

VCC

V

Mode Voltage

 

 

 

 

 

 

 

 

 

 

 

 

RRST

Reset Pull-down Resistor

 

50

300

kΩ

 

 

 

 

 

 

CIO

Pin Capacitance

Test Freq. = 1 MHz, TA = 25°C

 

10

pF

 

 

Active Mode, 12 MHz, VCC = 6V/3V

 

15/5.5

mA

 

Power Supply Current

 

 

 

 

 

Idle Mode, 12 MHz, VCC = 6V/3V

 

5/1

mA

ICC

 

P1.0 & P1.1 = 0V or VCC

 

 

 

 

 

 

Power-down Mode(2)

VCC = 6V, P1.0 & P1.1 = 0V or VCC

 

100

µA

 

 

 

 

 

 

VCC = 3V, P1.0 & P1.1 = 0V or VCC

 

20

µA

 

 

 

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 20 mA

Maximum total IOL for all output pins: 80 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

2. Minimum VCC for Power-down is 2V.

12 AT89C2051

0368G–MICRO–6/05

AT89C2051

18. External Clock Drive Waveforms

19. External Clock Drive

 

 

 

 

VCC = 2.7V to 6.0V

 

 

VCC = 4.0V to 6.0V

 

Symbol

 

Parameter

 

Min

Max

 

 

Min

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1/tCLCL

 

Oscillator Frequency

 

0

 

12

 

0

24

MHz

tCLCL

 

Clock Period

 

83.3

 

 

 

 

41.6

 

 

ns

tCHCX

 

High Time

 

30

 

 

 

 

15

 

 

ns

tCLCX

 

Low Time

 

30

 

 

 

 

15

 

 

ns

tCLCH

 

Rise Time

 

 

 

20

 

 

 

20

ns

tCHCL

 

Fall Time

 

 

 

20

 

 

 

20

ns

 

()

 

 

 

 

 

 

 

 

 

 

 

20. Serial Port Timing: Shift Register Mode Test Conditions

 

 

 

VCC = 5.0V ± 20%; Load Capacitance = 80 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 MHz Osc

 

Variable Oscillator

 

Symbol

Parameter

 

 

Min

Max

 

Min

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

tXLXL

Serial Port Clock Cycle Time

 

 

1.0

 

 

 

12 tCLCL

 

 

µs

tQVXH

Output Data Setup to Clock Rising Edge

 

 

700

 

 

 

10 tCLCL-133

 

 

ns

tXHQX

Output Data Hold after Clock Rising Edge

 

50

 

 

 

2 tCLCL-117

 

 

ns

tXHDX

Input Data Hold after Clock Rising Edge

 

 

0

 

 

 

0

 

 

ns

tXHDV

Clock Rising Edge to Input Data Valid

 

 

 

 

700

 

 

 

10 tCLCL-133

ns

13

0368G–MICRO–6/05

21. Shift Register Mode Timing Waveforms

22. AC Testing Input/Output Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.

23. Float Waveforms(1)

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.

14 AT89C2051

0368G–MICRO–6/05

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