
- •Features
- •1. Description
- •2. Pin Configuration
- •3. Block Diagram
- •4. Pin Description
- •4.3 Port 1
- •4.4 Port 3
- •4.6 XTAL1
- •4.7 XTAL2
- •5. Oscillator Characteristics
- •6. Special Function Registers
- •7. Restrictions on Certain Instructions
- •7.1 Branching Instructions
- •8. Program Memory Lock Bits
- •9. Idle Mode
- •10. Power-down Mode
- •11. Programming The Flash
- •12. Programming Interface
- •13. Flash Programming Modes
- •14. Flash Programming and Verification Characteristics
- •15. Flash Programming and Verification Waveforms
- •16. Absolute Maximum Ratings*
- •17. DC Characteristics
- •18. External Clock Drive Waveforms
- •19. External Clock Drive
- •20. Serial Port Timing: Shift Register Mode Test Conditions
- •21. Shift Register Mode Timing Waveforms
- •22. AC Testing Input/Output Waveforms(1)
- •23. Float Waveforms(1)
- •24. ICC (Active Mode) Measurements
- •25. ICC (Idle Mode) Measurements
- •26. ICC (Power Down Mode) Measurements
- •27. Ordering Information
- •27.1 Standard Package
- •28. Package Information

4.7XTAL2
Output from the inverting oscillator amplifier.
5. Oscillator Characteristics
The XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 5-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 5-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Figure 5-1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 5-2. External Clock Drive Configuration
4 AT89C2051
0368G–MICRO–6/05

AT89C2051
6. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Table 6-1. |
AT89C2051 SFR Map and Reset Values |
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0F8H |
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0F0H |
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B |
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00000000 |
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0E8H |
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0E0H |
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ACC |
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00000000 |
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0D8H |
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0D0H |
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PSW |
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00000000 |
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0C8H |
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0C0H |
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0B8H |
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IP |
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XXX00000 |
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0B0H |
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P3 |
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11111111 |
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0A8H |
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IE |
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0XX00000 |
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0A0H |
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98H |
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SCON |
SBUF |
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00000000 |
XXXXXXXX |
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90H |
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P1 |
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11111111 |
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88H |
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TCON |
TMOD |
TL0 |
TL1 |
TH0 |
TH1 |
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00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
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80H |
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SP |
DPL |
DPH |
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PCON |
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00000111 |
00000000 |
00000000 |
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0XXX0000 |
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0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
5
0368G–MICRO–6/05