
- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port C (PC5..PC0)
- •PC6/RESET
- •Port D (PD7..PD0)
- •RESET
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Operation
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Pin Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Power-save Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- •Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- •Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- •Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- •Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- •Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- •Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- •Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- •Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- •Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- •Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- •Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- •Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- •Table of Contents

Features
•High-performance, Low-power AVR® 8-bit Microcontroller
•Advanced RISC Architecture
–130 Powerful Instructions – Most Single-clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 16 MIPS Throughput at 16 MHz
–On-chip 2-cycle Multiplier
•Nonvolatile Program and Data Memories
–8K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
–512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
–1K Byte Internal SRAM
–Programming Lock for Software Security
•Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
–Real Time Counter with Separate Oscillator
–Three PWM Channels
–8-channel ADC in TQFP and MLF package
Eight Channels 10-bit Accuracy
–6-channel ADC in PDIP package Eight Channels 10-bit Accuracy
–Byte-oriented Two-wire Serial Interface
–Programmable Serial USART
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
•I/O and Packages
–23 Programmable I/O Lines
–28-lead PDIP, 32-lead TQFP, and 32-pad MLF
•Operating Voltages
–2.7 - 5.5V (ATmega8L)
–4.5 - 5.5V (ATmega8)
•Speed Grades
–0 - 8 MHz (ATmega8L)
–0 - 16 MHz (ATmega8)
•Power Consumption at 4 Mhz, 3V, 25°C
–Active: 3.6 mA
–Idle Mode: 1.0 mA
–Power-down Mode: 0.5 µA
8-bit with 8K Bytes In-System Programmable Flash
ATmega8
ATmega8L
2486O–AVR–10/04

Pin Configurations
PDIP
(RESET) PC6 |
|
1 |
28 |
|
PC5 (ADC5/SCL) |
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(RXD) PD0 |
|
2 |
27 |
|
PC4 (ADC4/SDA) |
(TXD) PD1 |
|
3 |
26 |
|
PC3 (ADC3) |
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(INT0) PD2 |
|
4 |
25 |
|
PC2 (ADC2) |
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(INT1) PD3 |
|
5 |
24 |
|
PC1 (ADC1) |
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(XCK/T0) PD4 |
|
6 |
23 |
|
PC0 (ADC0) |
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VCC |
|
7 |
22 |
|
GND |
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GND |
|
8 |
21 |
|
AREF |
|
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(XTAL1/TOSC1) PB6 |
|
9 |
20 |
|
AVCC |
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(XTAL2/TOSC2) PB7 |
|
10 |
19 |
|
PB5 (SCK) |
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(T1) PD5 |
|
11 |
18 |
|
PB4 (MISO) |
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(AIN0) PD6 |
|
12 |
17 |
|
PB3 (MOSI/OC2) |
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(AIN1) PD7 |
|
13 |
16 |
|
PB2 (SS/OC1B) |
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(ICP1) PB0 |
|
14 |
15 |
|
PB1 (OC1A) |
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TQFP Top View
|
PD2 (INT0) |
PD1 (TXD) |
PD0 (RXD) |
|
PC6 (RESET) |
PC5 (ADC5/SCL) |
PC4 (ADC4/SDA) |
PC3 (ADC3) |
PC2 (ADC2) |
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32 |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
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(INT1) PD3 |
1 |
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24 |
PC1 (ADC1) |
(XCK/T0) PD4 |
2 |
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23 |
PC0 (ADC0) |
GND |
3 |
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22 |
ADC7 |
VCC |
4 |
|
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21 |
GND |
GND |
5 |
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20 |
AREF |
VCC |
6 |
|
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19 |
ADC6 |
(XTAL1/TOSC1) PB6 |
7 |
|
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18 |
AVCC |
(XTAL2/TOSC2) PB7 |
8 |
|
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17 |
PB5 (SCK) |
|
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
|
|
(T1) PD5 |
(AIN0) PD6 |
(AIN1) PD7 |
|
(ICP1) PB0 |
(OC1A) PB1 |
(SS/OC1B) PB2 |
(MOSI/OC2) PB3 |
(MISO) PB4 |
|
(INT1) PD3 1 (XCK/T0) PD4
2 GND
3 VCC
4 GND
5 VCC
6
(XTAL1/TOSC1) PB6 7 (XTAL2/TOSC2) PB7
8
MLF Top View
PD2 (INT0) |
PD1 (TXD) |
PD0 (RXD) |
|
PC6 (RESET) |
PC5 (ADC5/SCL) |
PC4 (ADC4/SDA) |
PC3 (ADC3) |
PC2 (ADC2) |
|
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32 |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
(T1) PD5 |
(AIN0) PD6 |
(AIN1) PD7 |
(ICP1) PB0 |
(OC1A) PB1 |
(SS/OC1B) PB2 |
(MOSI/OC2) PB3 |
(MISO) PB4 |
24 PC1 (ADC1)
23 PC0 (ADC0)
22 ADC7
21 GND
20 AREF
19 ADC6
18 AVCC
17 PB5 (SCK)
NOTE:
The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.
2 ATmega8(L)
2486O–AVR–10/04