Статьи основные / % 1999 Base science and TCAD

JBasic. Dabrowski,Germany;ScienceSemiconductoH.-andJ. Mussig,ChallengesM. Duane,() in bProcessS. T. DunhamSimulationc, R. Goossensd,

H.-H. Vuong

r

Walter-Korsing-Stra e 2, D-15230 Frankfurt

Institute fo

and Comp

ter Engine ring

Dept.Physics,Boston UniversityAustin,Boston, MA

02215, USA;

(O er),

b

Advanced Micro Devices, Inc.,

Texas, USA;

c

Semiconducto

Research Corporation, National Semiconductor Corporation;ElectricalBel

Laboratories, Lucent T chnologies, Murray Hill, NJ 07944, USA

w

CMOS

Summary: We intend to turn the reader's attention

(Comp ementary Metal-Oxide-

r), the

mainstreamardsemicon-

may fail. Th

calls for

Semiconducttrol of at mistic

processes. W

r

ductor technology. W thin a decade, silicon CMOS devices will be 200

atoms

long and 50

toms deep. Of 50

billiony f

devices on a

hip only 64

needs of CMOS. It is

otedextremehat

which adopt meth-

researc

top cs in b

sic

a er als s ience which are likely to ma c

view

schemes to easily

solvable continuum equationsmodelsu t be constructed.

1

ods ranging from

quantum mechanihierarcthroughs

clas ical and Mon

Carlo

Introduction

ts of ma

Atomic-scale studies of solid state systems mark major achi v

terials science. The

ream microchip technology, Compl

emen

itiv

ss of

(Fig.mains1), tom stic

h and modeling

nhance compet-

by

ng techno progic t

ideas on funda

al lev Metal.

Oxide-Semicon

ctor (CMOS), may also

from them. Stimula edtaryb

CMOS

A

tec

nologistproductionfte nds

researcat cro sroad. Ph

insigh

can

one

h

h

ice of

directiontesto head, he ping in early devysical

t phasesguide. Th

miniaturizationbe bene cial

f

ilure and senhimselfitivitsupplyanalysis within

the exis

ng technologies.

same insi h

a scienti to

e cien simulatiopmenmodels. This can

Starting

frompositionsverview of CMOS, w

discuss

simulati

en

ocused

di crystalu ion-relat d problems viewed

om the perspectiv

of the whole

CAD tools,

growth, wafer processing, impl

tation,

di usion,

xid t,

This

ummarizes the 182nd H raeus-Seminar \Interna

W

vironmenChal-

silicides,lenge in Predict vprocesses,Proc

Simulation", ChiPPS'97 [1, 2], whicorkshopwasprimari y

fabrication process.

These issues are posted for rankingtionalthe

Internet [2].

back end

g tt ring, and prospectiv

metrologies and theories.

Figure 1

drives

chnology into the atomic

. In this STM

image of the clean S (001), atomic details as dimer rows, defects, and monatomic

steps are

clearlyMiniaturizationvis ble. The

length of the scanned area is 0regime.1 . Within one

2

decade, his will be the minimum feature

size of state-of-the-art CMOS devices.

MOS technology

is the Field E ect Transistor (MOSFET)

The workhorse of MOS tec

Fig. 2). Basically, it is a swhnologytccontrolled

y the gate potential. MOSFETs re

named after the type of carriers which ow b

w en the source (S) and the

D): nMOSFETs are built on p-doped material, with n

+

-doped source

drain

(S/D), while pMOSFETs are built

-doped

with p

+

-dopeand S/D.

Circuits must be fa ter, cost less per bit,

less power. T ey are c eap

er

with

terconn cts

hip. Hence

[4]: shor er channels,

oxides, shallo

e

. Gate oxideminiaturizationthicknesssubstrates,now 8 nm, will be thinn3

by 2001, wi

roug

ness approaching the

ox

t [3]. Estim

fro

step

1997 indicated

junctionscan be scaled downatomic2

[5]; inheigh same year

0.06 m

MOSFET

ox

ed [6]. Suc

trantesistors

thatof only 1.2 nm (12 A) was denm

work fast butwith

ox

tun eling through the oxide.

v high standby power losses d

Maintaining an increas

perfo mance of

ub-

MOSFETs may be expen

siv

[7]. Also costs of

billion

lines escal

te:

currenstrat

thegenerationrev

\f

b" (fac-

ry)

sts

around

dolla

. Only

a

fraction

of

y

th

c me from

utting-edgeproductionhnologie

(today 0.25

linewidth, or the

mate

xi

length, whi h

the

hannel length). Even 95% of the productus

shipped

1997somewhatby

microprocessor

ompany y havuebeen made

with

0.5 and 0.8 proc sses. Inde d,

ow has its c allenges,

A

which makeprosperingyestxceedsday's technologies cheaptomorrmay e welcome today.

ypical in

circuit needs severalthoughundred

teps whic

pply\old"position,

xidation, implantation, etching, polishing. The

wafer

by ocal doping and

.

Thenfabricationgate

are grown

innovationsnd co e

ytegratedgalithographysilicon,po

tacts are made, inte conn xidesare add d. It

remainis to

break the wafer into conhips and seal them

for protection. The steps

needed tostructuredmak the devices are na

ed FronisolationEnd Of the Line (FEOL) processes,

source

gate

drain

cross

ga

xide

FEOL. termi

But the road from physics to tec

Most\channel"S/Dare

inv

on channel

sub trate

gat(Dthek.,

wn)

also.heavilyAtheymbolizeprocessgate2highlytheisolationbetwAdpotgateschematiceendopedsteps\bird'stialpolySixideacerand.greateareThebeaks",(DSiO\stin. rThesubstrateeldip;-BEOLthan2sectionorsidetheelectrodesxide"Sithe-3othandNofbth4ectsor)a wesholdMtheyFelearehicOofX)nSFETtrodes,LOCOScontactedare.encompasvolandriangtheage,[8]sourceD.primaryBlackxidationVblarTes,siliciope(S)theareasnsd.andyieldgateAlsoppositelyati(notonconducting.drain-Thenslimiterstheshoofblsides

FmarkofOXigureshownthe

is

I plan ed

atoms

re activated

to

ubstitutional sites b

anneali g

Standard dopants are B, P, and As; new designshortery emplo

In and Sb. Implants

are s ot

hroughdopanpro

e SiOhnologyla er, someti

es

vered b

Si N . This may

th n used for

junctions and

ts of

h

l pro les. Gates

be de

CMOS combi

es nMOS and pMOS on the same waften, usually pre-

with

reduce chann l

g. T makectiv shallower pro les, B is co

imp anted as BF .

B. The n-

ype

ells (\tubs") for pMOS are

. Low-energy impl nts

2

3

4

2

posited already doped, but they are usually implantedbecause device dopedarameters

are optimal when the gate andadjustmenth channel have the same

ork

.

grownbeaky high-temperature dryOxidation after striping the rem

ing padproducesxide.

containing gas. This LOCal

of

Silicon

(LOCOS) sc

[7]

deposition steps, may be

eeded in

future [10]. High-

y functiongate xides are

The activ

areas are iso ated by

x dation of the pad

xide in O-

\bird

" (Fig. 2), so Shallow Trenc

Isolation (STI),

whicheme

etch and

joined by vertic

W \plugs". T

thermalfutu material

nesCu [11]. Glasses (BPSGels")

(salicidation)

Ti, in the future

ybe Co.

The metalqualit

ks S , but not

After gate deposition and etch, con

cts are ma

by se

-alignaddsed licidation

SiO . The

lm is removed, leaving well-d

contacts.

The

rcuit withred with planes of ho izontal Al

(\metallization v

wires. New dielectrics

will be needed and even Cu mafacilitatesy hav to be replaced.

are used fornreactedisolion,

but their

h gh dielectric conste nedts d lay the

of electric signals (paras tic capacitances,

RC) and

cross-talkpropagationb wee

2

DRAM SIZE (BYTES)

PRODUCT/TECHNOLOGY SPECIFICATIONS

1M

1M

4M

16M

64M

256M

1G

4G

16G

64G

1

LOGIC DESIGN

CHANGE

0.1

BIT PER COST DRAM

FAN OUT

ARCHITECTURE

COST PER LOT ($)

CLOCK SPEED

LOGIC GATES

CLOCK SKEW

CHANGE

PHYSICAL DESIGN

SHEET RES.

TRANISTOR PLACEMENT

100k

THRESHOLD V.

GATE LENGTH

0.01

TARNSIT FREQ.

CHANGE

PROCESS DESIGN

OXIDE THICK.

TEMPERATURE

DRAM

cents)-(milli

DOPANT DISTR.

IMPLANT DOSE

CHANGE

PROCESS

10 − 3

NO

10k

PRODUCT

MET?

10 − 4

1985

1990

1995

2000

2005

2010

YES

YEAR

SHIP

F

3

Left: Pr

per bit (circl

, righ

ordinate) and cost per lot of 25 wafers

R

ht:

s, left

ce) for DRAM

v rsus the y

of introduction [9].

ordinatalization. Logic design trans ates the

productk

sp ci cations into

ates,re gisters,

tc., assuming

parameters as

ar

wit

in

ranges

squa

teed

by

the

physical

layou . T

latter

out ines

th

physical

(transistor placement, linewidths) which should ful clocl the

peearquests. Thestructureproces

3

design Productsts the physical

design

generationsto process

conditions.

ulation

Environmentargetsand TCAD tools

to the

.

of technological processes is incr asingly attractiv

wafers.

First,Simt can sav

time.

it can reduce processing costs of

N w generat ons are

veloped b

scaling the

ones; problems

are

Modelsolv

b

matrix experimSecond,ts. A tec

is of en

uned during

by varying

the

process

for some wafer lots (\splitexistinglo s"). If thesilicproduction,hange

wafers can be lost. By the year 2010, a lo

of 50 wafers

will cost nearly

million dollars (Fig. 3) and this w

ma

prov

too expensiv

or too slow.

A semi onductor fab acts as a

h may need

few mindustrythstoo

drastic,run batc

(Fig. 3). Simulation ccomputerhnologyv

within a few

ys,

so virtual

ts w uld be optimal. But th s maywhicrk

ly if all

design

tools are

experimpr dic ive. This ma

be di cult (Tab. 1), but any progress is certainly

elcome.

Simulation for

CMOS includ

equipmenresults

crystal growth,

CVD,

rapid th rmal and plasma processing), pr

ss

(di usion,

inter-

epitaxy

etching), and device

deling(physi s,

ac ion of devices, in

on, burnut). These

tivities

eed

tion,ex en

v

se coupled to physically soundmoddels.

Process modedesign,mplantag y

be assixidation,ste atab

tomistterconnects,the retical tools employing quantum mechanics

molecular

dynamics. Di usion or in

rfacial physics ap

ear

particu arly

suiteand

Applicationedictivanced TCAD control

Accuracyvery highneeded

proCommentsvidebably an elusivodelsgoal: : :

process cen

ring

high

optimizemacrofor

mature product

adverse m processling

use to extract coe cients

early exploration

medium

l

splits in proces ing of lots

failure analys

probable cause

t

learning and insight

low

high return on inves

Table 1

TCAD applications. The top

testitems get most attentiotmen, while

much useful work is done in the bottom thre

classes. See also [3, 12, 13, 15].

inate. As examples, one may

reacti n rates

nd

king

ts.

The key

omistic issues in

f r crystal growth and w fer pro-

about

efects

quoted h mogeneity. The mainstichallenges in the front

nd are are ted

to

opan

pro lesdelingshallow junc ions and short

a nel , an

cessingxcellent pl

yground for atomistic

physics. It is int iguing thatcoecombicien tion of

models (e.g., for h

h-concentrati

regime and

for defect-mediat

di usion)

remains

problemat c. Promising

for

-scale physics in back

nd are sur-

face processes du ing deposition and

tomiching. The sim

on methods

but

key paramet rs are di cult to get and little physics is

ilt into BEOL models.

Technology

Aided Design (TCAD) can beulatsed on man

problems

(Tab. 1). It

ust be e cient; physics is just one of the means to ac

exist,v this.

In early

dev

sim

gives

in igh

into technology direc-

and elucidatesComputerelopmen eractions

etween optional olu ions. A high return

inveonstm

can be

by getulationing appr

but

arly answers to the

right

ques

. The earlierphases,problem is ca ght, the

it to correct. onI

the late dev

obtainedphase, TCAD is useful for

optimization, sensitivity

a lysis, and diagnosis [16]. Such quantitativeoximateplicatioeasier

more demanding

(T . 1). Butelopmenv insigh

helps. E.g, und

standi

g of

processes

nables

pot

of processalone

bility and of p ocess-inducared v

.

A

tial for modeling is in new materials.

a lot of data on

existigreattechnologies, so extrapolations

usually work. Thereb

questi

with new materials, as Cu instead

f Al, or

ts for SiO ariations. An ther key

ea wh

basic physics may help is in

2

comean

. Any insightexistingth

provide

arly in the

of

ew

chnoloreplacemen

have

large impact.

Practical TCAD uses

nallyterfacesheap,

tinuum

. This tradi-

tional methodpredictionsis

achingcomputatioin defect-mediat d pro le

olution,

hemical

hysical rea tion modeling, pred

tivteequipmgiescont and

physics

and practical non-equilibriumdevelopmentransport. It is unclear when it widelsbreakmodeling,down

but technology advances fast and th

may happen before wpographev alize

. Discus-

fabprocess/deviceSpeequipmenialization

KnoTm inwledgeimplantatineededcompletefora ectsTCADdi usion;ow,

ocess/deviceTo in RTAphysics

analytical

SIMSknock-on; SRPprocessbe pressure

metrology

unce

ta

y in poly

calibrationxid thickness

electrical tests

eleust

versus optical

xide thickness

variation

fusion later [17]tation. T

during RTA is

di cult to measu

The[18], but 1 v

simulation

m

icalmitati

ns; gr

depend

.

fer tempera ure T

T

2

Knowledge needed

f

TCAD

implan

can a ect the

lengtho defect geence

nd thereby

he dif

duringable220 V AC line c

T

y 6

[19].calibrationThe beam

nergy can

SIMS

pro les [20]. SRP dep nds

probe pressure [21]. Poly linewidth andoltxide thick-

ness are di cult to

hangedasure;

1% change a ects the saturation currena ectby 1%.

o

which would reliablydimensionalex rap late 1D data re needed. When adopted

Considiscreteer t

exampltomistbe . First,

electrical

characteristic of tiny tr

nsistors

. A

c phy

s not easily integrable into the exi ting

a ected by tmodelsw - and three-

(2D and 3D) structural details [14].

Thare

tools and will hav

to

rst tran la ed to continuum models.

.

3D narro

-

nel e ct becomes

to the 2D

hort-channel

to the continuum formalism, they

canmparableused in

modern

ulators wh ehectal

Since 2D dopan

pro les cannot be properly me su

(section 10), di usion

low to de ne equations. Second, applications beyond 0.1 simwill need

[4].

models

of defects and

ts, with stochastic analysis of uctuatio

be

ated b

ts to experiments not

lw ys doable

und conditionsdiscreteclo

Optim lly, TCAD should

cor ect

haracte istics given any pro-

those inBute production. The

maelectricallso employ wrong as

umptions or

scriptionCalibra on is also

ypically andwhole

is simulated. If

ess ow.

the models hayieldumeopan rous, often obscure

. They

cto

in no physics. The predicivitmodelsy pends thus on the

parametershoic of

structures,

mterpretu sholdvalue,

one experimenust heck assumptions in the proce

d d vice

ula-

in

of

he

t, and in

experience of the user.

he th

voltage from the

subsequentuitiondevice analysis does not

match the

ion , the test structure

yout,becaused electrical m asuremenprocess. K wledge simany

M dels wi h physicaldi ycultmeaningful parame ers

with known windows for

understanding,

nd

process

c nditions

v

the last 20Somey importanrs. void confu-

t eir

variation are thus

favored. Calibrat on

trategies are

t. A

-

ar as is required (Tab. 2). Phys cs can help by systematizing this knowledge

chy of

mo

els

atomi tic to con

uum

is needed.

basic

ierar.g.,

for segregatio

from, ust be re-

tin light of advand es in metr logymodels,

sion, implementation of the examinedodels ust b

backward compatible; their phy ical

interpretation would assists users and vendors, adding value to TCAD tools.

4

for crystal growth and wafer processing

puri ies

grow

ust

Si base material with homogeneous

on

the

lt anproducetheir inc

rporation

to the

crystal. Givendistributincre imng

CrystModelsal ameters (a 300 mm technology fab is

built in Dresde

Germany),

of O

nd dopants. Mo

eling can be used to predict the

ransport of the

-

modeling

o

sid

heat

beingy conv ction,

and

radi ection. 3D gas conv ction and reactiontransfergasulation

will gain

(SiHCl H ) with the

sts of developme

will

and sim

mporta ce. But melt

improvement [22]. M dels for

dimensi

are

velopmconduction,p se.

conv

is turbulent and thre

l, and thus di cult to handle.