Книги2 / 1993 P._Lloyd,__C._C._McAndrew,__M._J._McLennan,__S._N
.pdf
R.W . Knepper et al. : Technology CAD at IBM |
45 |
Figure 15. Finite element mesh structure for a 3D trench-bounded FET model (per ~ef. 22).
The figure shows the finite element mesh for a trench-bounded MOSFET model [22], as might be found in a DRAM cell having a deep trench storage capacitor. FEDSS-generated doping distributions were mapped into the 3D FIELDAY device structure for this simulation. In this case the authors of [22J were interested in studying the tradeoff(s) between peak gate dielectric electric field (as it relates to device reliability) and the device electrical characteristics as a function of corner radius of curvature. Use of 3D modeling was essential for accurate prediction of electrical behavior due to the submicron features of the structure. Problems of this nature may typically require 25,000 and even up to 100,000 nodes. Such problems have been run on an IBM RS/6000 workstation with run times on the order of 15-30 minutes per dc bias point.
The predicted FET transfer characteristics for the device of Figure 15 are shown in Figure 16 for the case of 3.3 volts applied from drain to source.
R.W. Knepper et al.: Technology CAD at IBM |
47 |
attribute files from the FOXi 3D solid model and then computes a capacitance or resistance matrix as an output data file.
An example of the use of FOXi/FIERCE is shown in Figure 17 which contains a view of a typical FOXi panel showing the construction of a metalization BEOL (back-end-of-line) structure comprised of word lines and bit lines separated by an insulating dielectric.
Figure 17. FOXi panel showing construction of a 3D BEOL (back end of line) structure. The structure shows 3 levels of wiring and stud interconnect separated by dielectric isolation.
The upper left window entitled "Tree" shows the subblocks used to build up the solid model. The "View" window shows a perspective of the 3D finite element mesh for the structure. The user has complete flexibility in manipulating and rotating the structure shown in View by using the mouse to point to and adjust the circular, clock-like "control wheels" shown at the far right- hand-side. Two examples of solid structures are given in Figures 18 and 19. Figure 18 illustrates a 3D meshed structure comprised of two metal lines with an interconnecting stud via which is of use in simulating via resistance. Figure 19 shows a closeup of the BEOL metal line structure given in the View window of the FOXi panel in Fig. 17.
48 |
R.W. Knepper et al.: Technology CAD at IBM |
|
Figure IR. FOXi 3D meshed structure or 2 wires on adjacent wiring levels interconnected by a stud via .
Figure 19. Closeup anD interlevel wiring structure shown in the panel or Fig. 17.
This structure could be used to calculate the interlevel wiring capacitance between bit Jines and word lines on a prospective DRAM memory chip.
7.Parameter Extraction and Circuit Model Generation
The model generation procedure for obtaining MOSFET equivalent circuit models for circuit analysis in ASTAP/ASX or SPICE involves t.ypically parameter extraction techniques using as input either 2D FIELDAY simulation results or measured data, as was explained in Figure 2b. This can be accomplished since the MOSFET is still primarily a 2D device (excluding devices of very small width dimension where fringing fields and/or gate oxide tapering may necessitate 3D FIELDAY simulation). Consequently, the model generation procedure for MOSFET devices is actually a simpler task than that for bipolar devices and does not normally require constructing an elaborate 3D distributed model as part of the procedure.
R.W. Knepper et al.: Technology CAD at IBM |
53 |
10° SiGe LTE
ROB;;;;11 kr1/o
10-1 WB=600A
-Calculations
...--. |
10-2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
N E |
|
3 |
|
|
|
|
|
|
|
::l. |
10- |
|
|
|
|
|
|
|
|
~ |
|
|
|
|
|
|
|
|
|
E |
|
|
|
|
|
|
|
|
|
' - " |
10-<1- |
|
|
|
|
|
|
|
|
--ill0 |
|
|
|
|
|
|
|
||
-.,. 10-5 |
|
|
Si |
Ion |
Implant |
|
|
||
|
|
|
|
|
|
|
|||
|
10-6 |
|
|
10-17kfljo |
|
|
|||
|
|
|
(850-900'\) |
|
|
||||
|
|
|
|
|
|
|
|||
|
|
|
|
|
- |
- |
Calculations |
|
|
|
10--B LU..lu.&.I:.&.U...I.LI..u..L.I...I..I..IL.L.LI:.&.U...I.LI..LLL.LLL.L.l.l.lLU.I:.&.U.............I.LI..LLL.L.l.l.lu..u |
||||||||
|
|
0.5 |
0.6 |
0.7 |
0.8 |
|
0.9 |
1.0 |
1.1 |
|
|
|
|
VBE |
(volls) |
|
|
|
|
Figure 24. DMG model simulation results of dc IV characteristics versus experimental data for SiGe LTE-base and Si III-base NPN transistors [24].
The collector current enhancement for the SiGe HBT over the Si BJT is seen to be about a factor of 4 or 5 and is predicted successfully by the simulation results as shown in the figure. The small variation of collector current with base dose is also shown for the Si BJT device. The small difference in base current between the HBT and the BJT transistors is probably due to a small difference in the emitter polysilicon interface surface recombination velocity measured in the devices and assumed in the simulation. Finally, the predicted f, high frequency cutoff versus collector current is shown in Figure 25 and compared with experimental measurements (for the SiGe device), showing good agreement with a peak ft of about 55 GHz.