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16 P. Lloyd et al.: Technology CAD at AT&T

 

Epi

Emitter

Base Oxide

Tub

 

 

Parameter

Thickness

Dose

Etch

Dose

SID Anneal

RTA

 

Xl

X2

X3

X4

Xs

X6

'Cd

0.97

-0.05

0.28

-0.01

0.23

-0.05

it

-0.26

0.22

-0.91

0.02

0.15

0.11

~

-0.04

0.10

-0.96

-0.04

0.14

0.14

Wb

0.05

-0.22

0.95

-0.07

-0.11

-0.11

Pb

-0.05

0.22

-0.93

-0.04

0.18

0.15

Table 2. Correlation Coefficients Between BJT Electrical and Process Parameters

required for aggressive linear design. The resulting profiles, along with geometry specifications, are used as input to device simulators that generate DC, C - V and transient characteristics. These simulations are repeated for the various geometries, temperatures, and extreme processing cases. Parameter extraction tools are then used to create model parameter files used in circuit simulations. This approach gives predictive process characterizations, and enables silicon designers to evaluate a technology before it is completed. Early test wafers are then analyzed, and used as part of the process of ongoing verification and improvement of our TCAD system. This allows out tools to be used with some confidence to predict the behavior of next generation technologies.

Our simulation system is also coupled to manufacturing line measurement databases, to verify and monitor the system's predictive capability. Much of this verification is done using the statistical and graphical tools provided by the S language [37]. The manufacturing databases track production variations, which are plotted against control limits and the predictions from compact models. Statistical analyses and graphical reports are generated to ensure conformance to specifications, and to reduce design risk. Figure 8 shows a typical report, that summarizes process variations in Ion for a nominal length n-channel transistor. The left segment shows the trend over a six month period, the middle section shows individual measurements made during the last month, and the right segment is a Q - Q plot of data for the last month. Shaded regions represent the manufacturing limits, and the solid horizontal lines are the predictions from compact models generated for nominal and extreme cases.

For certain classes of circuits, the matching between n- and p-channel transistors is critical. Figure 9 shows a scatter plot of the threshold voltage for both n- and p-channel devices, for data from one month from the manufacturing database. The unshaded region, inside the box, represents 20" limits for the technology. The six sided polygon, drawn with a solid line, is the convex hull formed from the predicted compact model parameter files for the extreme processing cases, which are the vertices of the polygon. To maximize yield, the process is controlled so that the number of sample points falling within the convex hull is maximized.

20

P. Lloyd et al.: Technology CAD at AT&T

functions, such as circuit simulation, parameter extraction, and stand alone evaluation, are guaranteed to be consistent with each other.

Figure 11 shows playbacks of ASIM3, against PADRE data that was used for extraction in CAMELOT. The data is for an n-channel MOSFET of Lm =0.25JllD. The top left plot of figure 11 shows threshold characteristics, I d as a function of V gs for V ds = O. IV and Vbs=0.0,-0.6,-1.2 and -2.4V. The top right plot shows subthreshold characteristics, I d as a function of V gs for V ds=O.l, 1.0,2.0 and 3.0V and V bs=O.OV.

The bottom plots show triode-saturation

characteristics,

I d as

a function

of V ds for

V gs =0.5,1.0,1.5,2.0,2.5 and 3.0V and

Vbs=O.OV, on

both

linear and

logarithmic

scales.

 

 

 

 

We have used this system for the ASIM3 and AUSSIM MOSFET models, for many flavors of BIT models, for diode models, and for 3-terminal resistor models. We have found that the system greatly simplifies compact model development and implementation in ADVICE and CELERITY. All our new compact models are defined using the CAMELOT system.

5.Conclusion

TCAD is an essential part of technology development and technology characterization at AT&T. Critical to the success of our TCAD system is on-going tool improvement to ensure accuracy, robustness, and a practical approach to software and data compatibility. We also recognize that people are an important part of the overall system. Our TCAD system is evolving from separate point tools bound in shell scripts, that communicate via files, to integrated tools that are modules in a common extension language environment, that operate on common objects that represent the structures being simulated. This paper has presented the important aspects of this evolution.

Interoperability and compatibility of point tools and simulation data significantly simplifies the job of process characterization, and allows high level tasks such as optimization and sensitivity analysis to be used effectively during technology development. We have given examples of the use of our TCAD system for high level tasks.

Acknowledgements

We would like to thank R. V. Booth, W. T. Cochran, W. M. Coughran Jr., E. Grosse, H. K. Gummel, G. A. Howlett, P. A. Layman, S. Liu, L. W. Nagel, R. K. Smith, M. J. Thoma, G. Zaneski, and many other colleagues at AT&T Bell Laboratories for contributions to this work. The use of the AT&T Bell Laboratories DDL facility in Allentown is gratefully acknowledged.

P. Lloyd et at.: Technology CAD at AT&T

21

Ids (rnA)

...

Ids (rnA)

0.15

1E-

 

0.1

0.05

o

1

2

3

0.5

 

I1

o

 

1 ' ,

, , 1 '

, , , 1 '

, , , 1

, 1 '

,

 

 

 

Vgs (V)

 

Vgs (V)

 

 

 

 

 

 

.. data (PADRE)

 

 

 

 

 

 

-ASIM3

 

 

Ids (rnA)

 

 

 

Ids (rnA)

 

 

1

 

 

 

 

 

 

0.5

1E-

o

t I I I

I I I I '

I I I I

1E-

r-llIr-l,r-'r-l,r--Ir--,r--,..--,,--,'--1,--,,--,,--,,---"I

I I I

 

o

1

2

3

 

o

1

2

3

 

 

Vds (V)

 

 

 

 

Vds (V)

 

Figure 11. Data Fits of the ASIM3 Compact Model, L m =O. 25 11m

22

P. Lloyd et al.: Technology CAD at AT&T

References

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[12]J. D. Bude and R. K. Smith, "Phase Space Simplex Monte Carlo for Semiconductor Transport," Proc. Eighth Int!. Conf. on Hot Carriers in Semiconductors, Oxford, 1993.

[13]J. D. Bude and 1. C. Kizilyalli, "New Mechanism for Bipolar Degradation in Submicron BiCMOS," Proc. Symp. on VLSITechnology, 1993.

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[14]B. R. Chawla and H. K. Gummel, "A Boundary Technique for Calculation of Distributed Resistances," IEEE Trans. Electron Devices, vol. ED-17, no. 10, Oct. 1970.

[15]T. A. Lenahan, "Calculation of Transmission-Line Parameters for 2D IC Interconnects," AT&T Technical Memorandum 52174-120988-01, 1988.

[16]L. W. Nagel, "ADVICE for Circuit Simulation," Proc. ISCAS, Apr. 1980.

[17]H. K. Gummel and H. C. Poon, "An Integral Charge-Control Model for Bipolar Transistors," Bell Syst. Tech. J., vol. 49, no. 5, pp. 827-852, May 1970.

[18]G. M. Kull, L. W. Nagel, S.-W. Lee, P. Lloyd, E. J. Prendergast, and H. Dirks, "A Unified Circuit Model for Bipolar Transistors Including Quasi-Saturation Effects," IEEE Trans. Electron Dev., vol. 32, no. 6, pp. 1103-1113, Jun. 1985.

[19]C. C. McAndrew, "A Complete and Consistent ElectricalfThermal HBT Model," Proc. IEEE BCTM, pp. 200-203, Oct. 1992.

[20]S. Liu and L. W. Nagel, "Small-Signal MOSFET Models for Analog Circuit Design," IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 983-998, Dec. 1982.

[21]S.-W. Lee and R. C. Rennick, "A Compact IGFET MODEL-ASIM," IEEE Trans. Computer-Aided Design, vol. 7, no. 9, pp. 952-975, Sep. 1988.

[22]Y. Tsividis and K. Suyama, "MOSFET Modeling for Analog Circuit CAD: Problems and Prospects," Proc. CICC, pp. 14.1.1-14.1.6, May 1993.

[23]c. C. McAndrew, B. K. Bhattacharyya, and O. Wing, "A Single Piece, C~ Continuous MOSFET Model Including Subthreshold Conduction," IEEE Electron Device Lett., vol. 12, no. 10, pp. 565-567, Oct. 1991.

[24]K. Singhal, C. C. McAndrew, S. R. Nassif, and V. Visvanathan, "The CENTER Design Optimization System," AT&T Technical Journal, vol. 68, no. 3, pp. 7792, May/June 1989.

[25]H. K. Dirks, R. Erwe, J. L. Lentz, C. C. McAndrew, S. R. Nassif, E. J. Prendergast, and K. Singhal, "The Modeling and Optimization of GaAs HFET Structures," Proc. NASECODE VI, Dublin, Ireland, pp. 28-39, July 1989.

[26]P. Lloyd, "Application of Numerical Simulation in Modeling of IC Device Structures," in Proc. NASECODE III, Galway, 1983.

[27]E. J. Prendergast, "An Integrated Approach to Modeling," in Proc. NASECODE IV D bin, 1985.

L-OJ G. Booch, Object-Oriented Design with Applications, Benjamin-Cummings, 1991.

[29]S. G. Duvall, "An Interchange Format for Process and Device Simulation," IEEE Trans. Computer-Aided Design, vol. 7, no. 7, pp. 741-754,1988.

[30]F. Fasching, C. Fischer, S. Selberherr, H. Stippel, W. Tuppa, and H. Read, "A PIP implementation for TCAD purposes," Simulation of Semiconductor Devices